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1. 发明申请

US20170115342A1 Scan Chain Circuits In Non-Volatile Memory 有权
公开(公告)号：US20170115342A1
公开(公告)日：2017-04-27
申请号：US14919154
申请日：2015-10-21
申请人： SanDisk 3D LLC
发明人： Kesheng Wang
IPC分类号： G01R31/3177 , G01R31/317 , G11C16/04
CPC分类号： G11C16/0483 , G01R31/318536 , G11C16/08 , G11C16/32 , G11C29/1201 , G11C29/12015 , G11C29/32 , G11C29/50012 , G11C2211/5644 , G11C2211/5646
摘要： A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the number of bits having a predetermined binary value. Each scan block includes a single latch to transfer the corresponding bit and to indicate reset. The scan blocks are organized into groups. Each group is enabled by a corresponding token signal. The token signal for each group is asserted after each preceding scan block indicates a pass value. When enabled by its token signal, the first scan block in a group is reset by a first clock signal. A second scan block in the group is enabled for reset after the first scan block indicates the pass value. The second scan block in the group is reset by a second clock signal having pulses that precede corresponding pulses from the first clock signal.

2. 发明申请

US20160139828A1 INDEPENDENT SET/RESET PROGRAMMING SCHEME 有权
标题翻译：独立设置/复位编程方案
公开(公告)号：US20160139828A1
公开(公告)日：2016-05-19
申请号：US14547473
申请日：2014-11-19
申请人： SANDISK 3D LLC
发明人： Tianhong Yan , Tz-yi Liu
IPC分类号： G06F3/06
CPC分类号： G06F3/0616 , G06F3/061 , G06F3/0625 , G06F3/0634 , G06F3/0644 , G06F3/0659 , G06F3/0679 , G06F3/0688 , Y02D10/154
摘要： Methods for operating a non-volatile memory that includes a plurality of memory arrays in which each memory array of the plurality of memory arrays may independently perform a SET operation, a RESET operation, or a read operation are described. The ability to independently SET or RESET memory arrays allows a SET operation to be performed on a first set of memory cells within a first memory array at the same time as a RESET operation is performed on a second set of memory cells within a second memory array. In some cases, the first memory array may be associated with a first memory bay and the second memory array may be associated with a second memory bay. Each memory bay may include a memory array, read/write circuits, and control circuitry for determining memory cell groupings and programming memory cells within the memory array based on the memory cell groupings.
摘要翻译：描述了包括多个存储器阵列的非易失性存储器的方法，其中多个存储器阵列的每个存储器阵列可以独立地执行SET操作，RESET操作或读取操作。独立地设置或重置存储器阵列的能力允许在第一存储器阵列内的第一组存储器单元上执行SET操作，同时对第二存储器阵列中的第二组存储器单元执行复位操作。在一些情况下，第一存储器阵列可以与第一存储器托架相关联，并且第二存储器阵列可以与第二存储器托架相关联。每个存储器托架可以包括存储器阵列，读/写电路和用于基于存储器单元分组来确定存储器单元分组和编程存储器阵列内的存储器单元的控制电路。

3. 发明申请

US20160111517A1 DUAL GATE STRUCTURE 有权
标题翻译：双门结构
公开(公告)号：US20160111517A1
公开(公告)日：2016-04-21
申请号：US14519068
申请日：2014-10-20
申请人： SANDISK 3D LLC
发明人： Wei-Te Wu , Ming-Che Wu , Yung-Tin Chen
IPC分类号： H01L29/66 , H01L21/311 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L27/115 , H01L29/786 , H01L21/02
CPC分类号： H01L29/6675 , H01L21/02532 , H01L21/02595 , H01L21/31111 , H01L21/823885 , H01L27/0688 , H01L27/101 , H01L27/11526 , H01L27/11573 , H01L27/2454 , H01L27/249 , H01L29/4908 , H01L29/4916 , H01L29/4966 , H01L29/51 , H01L29/66484 , H01L29/66666 , H01L29/78648 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/1226 , H01L45/141 , H01L45/146 , H01L45/16
摘要： Methods for forming a dual gate structure for a vertical TFT are described. The dual gate structure may be formed by performing a first etching process that includes forming a first set of trenches by etching a first set of oxide pillars to a first depth and forming a second set of trenches by etching a second set of oxide pillars to a second depth higher than the first depth, forming a first set of gate structures within the first set of trenches, forming a second set of gate structures within the second set of trenches, performing a second etching process that includes forming a third set of trenches by etching the first set of gate structures from a second initial depth to a third depth and forming a fourth set of trenches by etching the second set of gate structures to a fourth depth higher than the third depth.
摘要翻译：描述了用于形成用于垂直TFT的双栅极结构的方法。可以通过执行第一蚀刻工艺来形成双栅极结构，所述第一蚀刻工艺包括通过将第一组氧化物柱蚀刻到第一深度并形成第二组沟槽来形成第一组沟槽，并通过将第二组氧化物柱蚀刻到第二深度高于第一深度，在第一组沟槽内形成第一组栅极结构，在第二组沟槽内形成第二组栅极结构，执行第二蚀刻工艺，其包括通过以下步骤形成第三组沟槽：将第一组栅极结构从第二初始深度蚀刻到第三深度，并通过将第二组栅极结构蚀刻到高于第三深度的第四深度而形成第四组沟槽。

4. 发明授权

US09318533B2 Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays 有权
标题翻译：减少3D ReRAM阵列开关特性的基于位置的变化的方法和系统
公开(公告)号：US09318533B2
公开(公告)日：2016-04-19
申请号：US14462374
申请日：2014-08-18
申请人： SANDISK 3D LLC
发明人： Pankaj Kalra , Chandrasekhar Gorla , Masaaki Higashitani
IPC分类号： H01L29/06 , H01L27/24 , H01L45/00 , H01L49/02 , H01L29/786
CPC分类号： H01L27/2481 , H01L27/2409 , H01L28/20 , H01L29/78642 , H01L31/0547 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/16 , Y02E10/52
摘要： Methods for reducing location-based variations in the switching characteristics of memory cells within a memory array are described. In some cases, the resistance of an embedded resistor within each memory cell may be set to reduce the overall variation in series resistances for the memory cells within a memory array. For example, embedded resistors associated with far-far bits may be set to a lower resistance than embedded resistors associated with near-near bits. An embedded resistor may comprise a layer of polysilicon within a memory cell. Selective ion implantation may be used to reduce the embedded resistor resistance for memory cells within a particular region of the memory array and to form two or more different sets of embedded resistors within the memory array.
摘要翻译：描述了用于减少存储器阵列内的存储器单元的开关特性的基于位置的变化的方法。在一些情况下，可以设置每个存储单元内的嵌入式电阻器的电阻以减小存储器阵列内的存储单元的串联电阻的总体变化。例如，与远近位相关联的嵌入式电阻器可以被设置为比与近近位相关联的嵌入式电阻器更低的电阻。嵌入式电阻器可以包括存储器单元内的多晶硅层。可以使用选择性离子注入来降低存储器阵列的特定区域内的存储器单元的嵌入式电阻器电阻并且在存储器阵列内形成两个或更多个不同的嵌入式电阻器组。

5. 发明授权

US09299928B2 Nonvolatile memory device having a current limiting element 有权
公开(公告)号：US09299928B2
公开(公告)日：2016-03-29
申请号：US14625867
申请日：2015-02-19
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Tony P. Chiang , Imran Hashim
IPC分类号： G11C11/00 , G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/56 , G11C2213/76 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/1616
摘要： Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

6. 发明授权

US09281029B2 Non-volatile memory having 3D array architecture with bit line voltage control and methods thereof 有权
标题翻译：具有具有位线电压控制的3D阵列架构的非易失性存储器及其方法
公开(公告)号：US09281029B2
公开(公告)日：2016-03-08
申请号：US13794344
申请日：2013-03-11
申请人： SanDisk 3D LLC
发明人： Raul Adrian Cernea
IPC分类号： G11C7/12 , G11C8/08 , G11C11/4094 , G11C5/02 , G11C7/18 , G11C13/00
CPC分类号： G11C7/12 , G11C5/025 , G11C7/18 , G11C8/08 , G11C11/4094 , G11C13/0021 , G11C13/004
摘要： In a 3D memory with vertical local bit lines, each local bit line is switchably connected to a node on a global bit line having first and second ends, the local bit line voltage is maintained at a predetermined reference level in spite of being driven by a bit line driver from a first end of the global bit line that constitutes variable circuit path length and circuit serial resistance. This is accomplished by a feedback voltage regulator comprising a voltage clamp at the first end of the global bit line controlled by a bit line voltage comparator at the second end of the global bit line. The comparator compares the bit line voltage sensed from the second end with the predetermined reference level and outputs a control voltage to control the voltage clamp In this way the voltage at the local bit line is regulated at the reference voltage.
摘要翻译：在具有垂直局部位线的3D存储器中，每个局部位线可切换地连接到具有第一和第二端的全局位线上的节点，局部位线电压被维持在预定的参考电平，尽管由全局位线第一端的位线驱动器构成可变电路路径长度和电路串联电阻。这是通过一个反馈电压调节器实现的，该电压调节器包括在由全局位线的第二端的位线电压比较器控制的全局位线的第一端的电压钳位。比较器将从第二端检测的位线电压与预定参考电平进行比较，并输出控制电压以控制电压钳位。以这种方式，局部位线处的电压被调节在参考电压。

7. 发明授权

US09246091B1 ReRAM cells with diffusion-resistant metal silicon oxide layers 有权
标题翻译： ReRAM电池具有耐扩散性的金属氧化硅层
公开(公告)号：US09246091B1
公开(公告)日：2016-01-26
申请号：US14338979
申请日：2014-07-23
申请人： Intermolecular Inc. , Kabushiki Kaisha Toshiba , SanDisk 3D LLC
发明人： Yun Wang , Federico Nardi
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L45/1253 , H01L27/24 , H01L27/2409 , H01L45/04 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1616
摘要： A metal silicon oxide barrier layer between a nitride electrode containing the same metal and an oxide variable-resistance layer in a ReRAM cell prevents the metal from diffusing into the variable-resistance layer and prevents oxygen from diffusing into and oxidizing the electrode. Compound oxides of the same metal and silicon with varying stoichiometries and metal/silicon ratios may optionally replace part or all of the variable-resistance layer, a defect-reservoir layer, or both. The metal nitride electrode may include a metal silicon nitride current-limiting portion. Optionally, all the layers sharing the common metal may be formed in-situ as part of a single unit process, such as atomic layer deposition.
摘要翻译：在ReRAM单元中含有相同金属的氮化物电极和氧化物可变电阻层之间的金属氧化硅阻挡层防止金属扩散到可变电阻层中，并防止氧气扩散到氧化电极。具有不同化学计量和金属/硅比的相同金属和硅的复合氧化物可任选地替代部分或全部可变电阻层，缺陷储层或两者。金属氮化物电极可以包括金属氮化硅限流部。可选地，共享公共金属的所有层可以原位形成为单个单元工艺的一部分，例如原子层沉积。

8. 发明授权

US09245599B1 Timed multiplex sensing 有权
公开(公告)号：US09245599B1
公开(公告)日：2016-01-26
申请号：US14887547
申请日：2015-10-20
申请人： SANDISK 3D LLC
发明人： Anurag Nigam , Gopinath Balakrishnan
IPC分类号： G11C13/00 , G11C7/08 , G11C16/26 , G11C16/04
CPC分类号： G11C7/08 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75
摘要： Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation.

9. 发明申请

US20160020389A1 SIDE WALL BIT LINE STRUCTURES 有权
标题翻译：侧墙线结构
公开(公告)号：US20160020389A1
公开(公告)日：2016-01-21
申请号：US14716382
申请日：2015-05-19
申请人： SANDISK 3D LLC
发明人： Perumal Ratnam , Christopher Petti , Tianhong Yan
IPC分类号： H01L45/00
CPC分类号： G11C13/004 , G06F11/1048 , G11C7/12 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0021 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , G11C2216/10 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/786 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/122 , H01L45/1226 , H01L45/1246 , H01L45/146
摘要： Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
摘要翻译：描述了在存储器操作期间通过存储器阵列的未选择的存储单元减少泄漏电流的方法。在一些情况下，可以通过将连接到未选择的存储器单元的可调电阻位线结构设置为非导通状态来减小通过存储器阵列的未选择存储单元的漏电流。可调电阻位线结构可以包括位线结构，其中可以通过向位线结构的选择栅极部分施加电压来调整位线结构的本征（或近固有）多晶硅部分的电阻其不直接连接到本征多晶硅部分。本征多晶硅部分可以基于施加到选择栅极部分的电压而被设置为导通状态或非导通状态。

10. 发明授权

US09227456B2 Memories with cylindrical read/write stacks 有权
标题翻译：具有圆柱读/写堆栈的记忆体
公开(公告)号：US09227456B2
公开(公告)日：2016-01-05
申请号：US13789375
申请日：2013-03-07
申请人： SanDisk 3D LLC
发明人： Henry Chien , Yao-Sheng Lee , George Samachisa , Johann Alsmeier
IPC分类号： G11C5/02 , B42D15/02 , H01L21/82 , G11C13/00 , H01L45/00 , H01L27/24 , A63F13/00
CPC分类号： B42D15/02 , A63F13/00 , G11C5/02 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C2213/71 , H01L21/82 , H01L27/2409 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1273 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1616
摘要： A three-dimensional memory is formed as an array of memory elements across multiple layers positioned at different distances above a semiconductor substrate. Cylindrical stacks of memory elements are formed where a cylindrical opening has read/write material deposited along its wall, and a cylindrical vertical bit line formed along its central axis. Memory elements formed on either side of such a cylinder may include sheet electrodes that extend into the read/write material.
摘要翻译：三维存储器形成为跨越位于半导体衬底上方不同距离的多个层的存储元件的阵列。形成存储元件的圆柱形堆叠，其中圆柱形开口具有沿其壁沉积的读/写材料，以及沿其中心轴线形成的圆柱形垂直位线。形成在这种气缸两侧的记忆元件可以包括延伸到读/写材料中的片电极。

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