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1. 发明授权

US09991254B1 Forming horizontal bipolar junction transistor compatible with nanosheets 有权
公开(公告)号：US09991254B1
公开(公告)日：2018-06-05
申请号：US15454248
申请日：2017-03-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Juntao Li , Geng Wang , Qintao Zhang
IPC分类号： H01L27/06 , H01L21/8249 , H01L29/06 , H01L29/66 , H01L21/02 , H01L29/165 , H01L27/07
CPC分类号： H01L27/0623 , H01L21/8249 , H01L27/0635 , H01L27/0711 , H01L27/0722 , H01L29/0673 , H01L29/165 , H01L29/66227 , H01L29/66545 , H01L29/66553 , H01L29/775 , H01L29/785
摘要： A semiconductor device includes a substrate and a field effect transistor (FET) arranged on the substrate. The FET includes a gate positioned on the substrate. The gate includes a nanosheet extending through a channel region of the gate. The FET includes a pair of source/drains arranged on opposing sides of the gate. The semiconductor device further includes a bipolar junction transistor (BJT) arranged adjacent to the FET on the substrate. The BJT includes an emitter and a collector. The BJT includes a nanosheet including a semiconductor material extending from the emitter to the collector, with a doped semiconductor material arranged above and below the nanosheet.

2. 发明授权

US09240451B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US09240451B2
公开(公告)日：2016-01-19
申请号：US14485572
申请日：2014-09-12
申请人： FUJI ELECTRIC CO., LTD.
发明人： Fumikazu Imai
IPC分类号： H01L27/095 , H01L29/47 , H01L21/00 , H01L21/338 , H01L29/16 , H01L29/872 , H01L29/66 , H01L29/06 , H01L21/04 , H01L29/40 , H01L29/45 , H01L29/04
CPC分类号： H01L29/1608 , H01L21/0495 , H01L29/045 , H01L29/0619 , H01L29/401 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/66227 , H01L29/872
摘要： A silicon carbide semiconductor device includes a low-concentration n-type drift layer deposited on a silicon carbide substrate to form a semiconductor substrate. A first front surface metal layer, which forms a Schottky contact with the semiconductor substrate, is formed on a front surface of the semiconductor substrate. An outer circumferential end of the first front surface metal layer extends on an interlayer insulating film which covers an edge portion. A second front surface metal layer which forms a front surface electrode is formed on the first front surface metal layer. When a portion of the second front surface metal layer is formed by dry etching, the entire first front surface metal layer, which will be Schottky contact metal, is covered with the second front surface metal layer. Thus, generation of an etching residue is prevented and a device with a front surface electrode structure with high reliability is provided.
摘要翻译：碳化硅半导体器件包括沉积在碳化硅衬底上以形成半导体衬底的低浓度n型漂移层。与半导体衬底形成肖特基接触的第一表面金属层形成在半导体衬底的前表面上。第一前表面金属层的外周端在覆盖边缘部分的层间绝缘膜上延伸。形成前表面电极的第二前表面金属层形成在第一前表面金属层上。当通过干法蚀刻形成第二前表面金属层的一部分时，将第二前表面金属层覆盖作为肖特基接触金属的整个第一前表面金属层。因此，防止产生蚀刻残渣，并提供具有高可靠性的具有前表面电极结构的器件。

3. 发明授权

US09768260B2 Fabrication method of silicon carbide semiconductor apparatus and silicon carbide semiconductor apparatus fabricated thereby 有权
公开(公告)号：US09768260B2
公开(公告)日：2017-09-19
申请号：US14388729
申请日：2013-03-14
申请人： FUJI ELECTRIC CO., LTD.
发明人： Akimasa Kinoshita , Takashi Tsuji , Kenji Fukuda
IPC分类号： H01L29/45 , H01L21/28 , H01L29/16 , H01L21/04 , H01L29/47 , H01L29/872 , H01L29/66 , H01L21/02
CPC分类号： H01L29/1608 , H01L21/02068 , H01L21/02529 , H01L21/02609 , H01L21/0485 , H01L21/0495 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/66227 , H01L29/872
摘要： Process (A) of preparing a silicon carbide substrate of a first conductivity type; process (B) of forming an epitaxial layer of the first conductivity type on one principal surface of the silicon carbide substrate; process (C) of forming on another principal surface of the silicon carbide substrate, a first metal layer; process (D) of heat treating the silicon carbide substrate after the process (C) to form an ohmic junction between the first metal layer and the other principal surface of the silicon carbide substrate, and a layer of a substance (10) highly cohesive with another metal on the first metal layer; and a process (E) of removing impurities and cleaning a surface of the first metal layer (8) on the other principal surface of the silicon carbide substrate (D), are performed. The heat treatment at process (D) is executed at a temperature of 1,100 degrees C. or more.

4. 发明申请

US20120298963A1 STRUCTURE FOR USE IN FABRICATION OF PIN HETEROJUNCTION TFET 审中-公开
标题翻译：用于制造PIN异构TFET的结构
公开(公告)号：US20120298963A1
公开(公告)日：2012-11-29
申请号：US13571392
申请日：2012-08-10
申请人： Sarunya Bangsaruntip , Steven Koester , Isaac Lauer , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Steven Koester , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/772
CPC分类号： H01L29/7391 , H01L21/2007 , H01L21/76254 , H01L29/66227
摘要： A structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes a silicon wafer comprising an alignment trench, a p-type silicon germanium (SiGe) region, and a hydrogen implantation region underneath the p-type SiGe region and the alignment trench that divides the silicon wafer into a upper silicon region and a lower silicon region, wherein the upper silicon region comprises the alignment trench and the p-type SiGe region; and a first oxide layer located over the alignment trench and the p-type SiGe region that fills the alignment trench and is bonded to a second oxide layer located on a handle wafer; wherein the alignment trench is configured to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region.
摘要翻译：用于制造PiN异质结隧道场效应晶体管（TFET）的结构包括：硅晶片，其包括对准沟槽，p型硅锗（SiGe）区域和p型SiGe区域下方的氢注入区域，以及所述对准沟槽将所述硅晶片分成上硅区域和下硅区域，其中所述上硅区域包括所述对准沟槽和所述p型SiGe区域; 以及位于对准沟槽和p型SiGe区域上方的第一氧化物层，其填充对准沟槽并且结合到位于处理晶片上的第二氧化物层; 其中所述对准沟槽被配置为将包括所述PiN异质结TFET的器件的布线电平对准到所述p型SiGe区域。

5. 发明授权

US5465001A Electronic component capable of negative dynamic resistance 失效
标题翻译：具有负动态电阻的电子元件
公开(公告)号：US5465001A
公开(公告)日：1995-11-07
申请号：US178574
申请日：1994-01-07
申请人： Tomasz Skotnicki , Gerard Merckel
发明人： Tomasz Skotnicki , Gerard Merckel
IPC分类号： H01L21/822 , H01L21/33 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L29/66 , H01L29/732 , H01L29/739 , H01L29/70 , H01L29/73
CPC分类号： H01L29/66227 , H01L21/8249 , H01L29/732 , H01L29/739 , Y10S257/90
摘要： The semiconductor electronic component comprises, within a semiconductor substrate (3), a first active region (2,4) having a first type of conductivity (n, n.sup.++), and a second active region (10), having a second type of conductivity (p, p.sup.++), opposite that of the first type, located between the first active region (2) and the upper face (5) of the substrate. A projecting region (6), containing a third active region (7, 8) having the first type of conductivity (n.sup.+, n.sup.++) and surmounting a first part (10a) of the second active region, is provided on the upper face of the substrate. Metallizations (13, 14, 15) are respectively located in contact with the three active regions (4, 10e, 7). The second active region includes a depletable semiconductor zone (Z) extending outside the first part (10a) of the second active region, and between the first active region (2) and the upper face (5) of the substrate. Depletion means (11; 213b, 209b, 211), located in the immediate vicinity of this depletable zone (Z) and suitable for depleting the said depletable zone under the action of a selected bias voltage, are also provided.
摘要翻译：半导体电子部件包括在半导体衬底（3）内具有第一导电类型（n，n ++）的第一有源区（2,4）和具有第二类导电性的第二有源区（10）（p，p ++）与位于第一有源区域（2）和衬底的上表面（5）之间的与第一类型相反的方向。包含具有第一类型导电性（n +，n + +）并覆盖第二活性区域的第一部分（10a）的第三有源区域（7,8）的突出区域（6）设置在第二有源区域基质。金属化（13,14,15）分别与三个有源区域（4,10e，7）接触。第二有源区包括延伸到第二有源区的第一部分（10a）外部以及在第一有源区（2）和衬底的上表面（5）之间的可消耗的半导体区（Z）。也提供位于该可消耗区域（Z）附近并且适合于在选定的偏置电压的作用下耗尽所述可消耗区域的消耗装置（11; 213b，209b，211）。

6. 发明申请

US20180342578A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180342578A1
公开(公告)日：2018-11-29
申请号：US15916423
申请日：2018-03-09
申请人： Tsinghua University , HON HAI PRECISION INDUSTRY CO., LTD.
发明人： JIN ZHANG , YANG WEI , KAI-LI JIANG , SHOU-SHAN FAN
IPC分类号： H01L29/06 , H01L51/00 , H01L29/423 , H01L29/16 , B82Y30/00 , H01L21/02
CPC分类号： H01L29/0673 , B82Y10/00 , B82Y30/00 , H01L21/02425 , H01L21/02444 , H01L21/02488 , H01L21/02491 , H01L21/02502 , H01L21/02513 , H01L21/02521 , H01L21/02631 , H01L27/04 , H01L29/1608 , H01L29/413 , H01L29/41733 , H01L29/41741 , H01L29/42312 , H01L29/66227 , H01L29/78687 , H01L51/0048 , H01L51/0562
摘要： A semiconductor device includes a gate electrode, an insulating layer, a first carbon nanotube, a second carbon nanotube, a P-type semiconductor layer, an N-type semiconductor layer, a conductive film, a first electrode, a second electrode and a third electrode. The insulating layer is located on a surface of the gate electrode. The first carbon nanotube and the second carbon nanotube are located on a surface of the insulating layer. The P-type semiconductor layer and the N-type semiconductor layer are located on the surface of the insulating layer and apart from each other. The conductive film is located on surfaces of the P-type semiconductor layer and the N-type semiconductor layer. The first electrode is electrically connected with the first carbon nanotube. The second electrode is electrically connected with the second carbon nanotube. The third electrode is electrically connected with the conductive film.

7. 发明授权

US09926193B2 Magnetic nanomechanical devices for stiction compensation 有权
公开(公告)号：US09926193B2
公开(公告)日：2018-03-27
申请号：US15301337
申请日：2014-06-27
申请人： Intel Corporation
发明人： Jorge A. Munoz , Dmitri E. Nikonov , Kelin J. Kuhn , Patrick Theofanis , Chytra Pawashe , Kevin Lin , Seiyon Kim
IPC分类号： B82B1/00 , B82B3/00 , H01L29/66 , H01L29/84 , H01L29/82 , H01H59/00 , B82Y15/00 , B82Y25/00 , B82Y40/00
CPC分类号： B82B1/005 , B81B3/0016 , B81B7/02 , B81B2201/014 , B81B2203/0118 , B82B1/002 , B82B3/0023 , B82Y15/00 , B82Y25/00 , B82Y40/00 , H01H1/0094 , H01H1/54 , H01H59/0009 , H01L29/66227 , H01L29/82 , H01L29/84 , Y10S977/732 , Y10S977/838 , Y10S977/888 , Y10S977/938
摘要： Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.

8. 发明申请

US20160380098A1 DOUBLE EXPONENTIAL MECHANISM CONTROLLED TRANSISTOR 有权
标题翻译：双重指导机制控制晶体管
公开(公告)号：US20160380098A1
公开(公告)日：2016-12-29
申请号：US14836054
申请日：2015-08-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd. , National Taiwan University
发明人： Jenn-Gwo Hwu , Samuel C. Pan , Chien-Shun Liao
IPC分类号： H01L29/78 , H01L29/417 , H01L21/28 , H01L29/66 , H01L21/306 , H01L21/283 , H01L29/423 , H01L29/45
CPC分类号： H01L29/7827 , H01L21/28176 , H01L21/283 , H01L21/30604 , H01L29/0895 , H01L29/417 , H01L29/41741 , H01L29/41775 , H01L29/423 , H01L29/42368 , H01L29/42376 , H01L29/45 , H01L29/66227 , H01L29/66666 , H01L29/72 , H01L29/76
摘要： The present disclosure relates to a tunnel FET device with a steep sub-threshold slope, and a corresponding method of formation. In some embodiments, the tunnel FET device has a dielectric layer arranged over a substrate. A conductive gate electrode and a conductive drain electrode are arranged over the dielectric layer. A conductive source electrode contacts the substrate at a first position located along a first side of the conductive gate electrode. The conductive drain electrode is arranged at a second position located along the first side of the conductive gate electrode. By arranging the conductive gate electrode over the dielectric layer at a position laterally offset from the conductive drain electrode, the conductive gate electrode is able to generate an electric field that controls tunneling of minority carriers, which can change the effective barrier height of the tunnel barrier, and thereby improving a sub-threshold slope of the tunnel FET device.
摘要翻译：本公开涉及具有陡峭的次阈值斜率的隧道FET器件和相应的形成方法。在一些实施例中，隧道FET器件具有布置在衬底上的电介质层。导电栅电极和导电漏极布置在电介质层的上方。导电源电极在沿着导电栅电极的第一侧定位的第一位置处接触基板。导电漏极布置在沿着导电栅电极的第一侧定位的第二位置处。通过在导电栅电极横向偏移的位置上布置导电栅电极，导电栅极能够产生控制少数载流子的隧道的电场，这可以改变隧道势垒的有效势垒高度，从而提高隧道FET器件的次阈值斜率。

9. 发明申请

US20150311305A1 SPIN MOSFET 审中-公开
公开(公告)号：US20150311305A1
公开(公告)日：2015-10-29
申请号：US14793173
申请日：2015-07-07
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Mizue ISHIKAWA , Tomoaki INOKUCHI , Hideyuki SUGIYAMA , Tetsufumi TANAMOTO , Yoshiaki SAITO
IPC分类号： H01L29/45 , H01L29/82 , H01L29/08 , H01L29/66
CPC分类号： H01L29/45 , G11C11/161 , H01L29/0847 , H01L29/0895 , H01L29/41725 , H01L29/66227 , H01L29/66984 , H01L29/82
摘要： An MOSFET according to an embodiment includes: a source and drain electrodes each including a magnetic layer; a gate insulating film; and a gate electrode provided on the gate insulating film, a junction resistance on a source electrode side being greater than that on a drain electrode side, when the MOSFET is of n-channel type, the source and drain electrodes contain a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is greater than that between the Fermi surface and a conduction band minimum, and when the spin-transfer-torque switching MOSFET is of p-channel type, the source and drain electrodes containing a magnetic material in which a gap energy between a Fermi surface and a valence band maximum is less than that between the Fermi surface and a conduction band minimum.
摘要翻译：根据实施例的MOSFET包括：源极和漏极，每个包括磁性层; 栅极绝缘膜; 以及设置在所述栅极绝缘膜上的栅电极，在所述MOSFET为n沟道型时，所述源电极侧的结电阻大于所述漏电极侧的结电阻，所述源电极和漏极包含磁性材料，其中，费米表面和价带最大值之间的间隙能量大于费米表面和导带最小值之间的间隙能量，并且当自旋转移 - 转矩开关MOSFET是p沟道型时，源极和漏极包含费米表面和价带最大值之间的间隙能量小于费米表面和导带最小值之间的磁性材料。

10. 发明申请

US20150056786A1 FABRICATION METHOD OF SILICON CARBIDE SEMICONDUCTOR APPARATUS AND SILICON CARBIDE SEMICONDUCTOR APPARATUS FABRICATED THEREBY 有权
标题翻译：硅碳化硅半导体器件和碳化硅半导体器件的制造方法
公开(公告)号：US20150056786A1
公开(公告)日：2015-02-26
申请号：US14388729
申请日：2013-03-14
申请人： FUJI ELECTRIC CO., LTD.
发明人： Akimasa Kinoshita , Takashi Tsuji , Kenji Fukuda
IPC分类号： H01L29/16 , H01L29/66 , H01L29/47 , H01L21/02 , H01L21/04
CPC分类号： H01L29/1608 , H01L21/02068 , H01L21/02529 , H01L21/02609 , H01L21/0485 , H01L21/0495 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/66227 , H01L29/872
摘要： Process (A) of preparing a silicon carbide substrate of a first conductivity type; process (B) of forming an epitaxial layer of the first conductivity type on one principal surface of the silicon carbide substrate; process (C) of forming on another principal surface of the silicon carbide substrate, a first metal layer; process (D) of heat treating the silicon carbide substrate after the process (C) to form an ohmic junction between the first metal layer and the other principal surface of the silicon carbide substrate, and a layer of a substance (10) highly cohesive with another metal on the first metal layer; and a process (E) of removing impurities and cleaning a surface of the first metal layer (8) on the other principal surface of the silicon carbide substrate (D), are performed. The heat treatment at process (D) is executed at a temperature of 1,100 degrees C. or more.
摘要翻译：制备第一导电类型的碳化硅衬底的工艺（A）; 在碳化硅衬底的一个主表面上形成第一导电类型的外延层的工艺（B）; 在碳化硅衬底的另一个主表面上形成第一金属层的工艺（C）; （C）之后热处理碳化硅衬底以在第一金属层与碳化硅衬底的另一个主表面之间形成欧姆结的工艺（D），以及一层与第一金属层上的另一种金属; 以及在碳化硅衬底（D）的另一个主表面上除去杂质并清洁第一金属层（8）的表面的工艺（E）。处理（D）的热处理在1100℃以上的温度下进行。

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