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41. 发明申请

US20170084326A1 A NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY 审中-公开
公开(公告)号：US20170084326A1
公开(公告)日：2017-03-23
申请号：US15126255
申请日：2014-07-08
申请人： Daniel H. Morris , Uygar E. Avci , Rafael Rios , Ian A. Young
发明人： Daniel H. Morris , Uygar E. Avci , Rafael Rios , Ian A. Young
IPC分类号： G11C11/38 , H01L27/105 , H01L27/102 , G11C11/412
CPC分类号： G11C11/38 , G11C11/404 , G11C11/412 , H01L27/102 , H01L27/1021 , H01L27/1052 , H01L29/7391 , H01L29/885
摘要： Described is a memory bit-cell comprising: a storage node; an access transistor coupled to the storage node; a capacitor having a first terminal coupled to the storage node; and one or more negative differential resistance devices coupled to the storage node such that the memory bit-cell is without one of a ground line or a supply line or both.

42. 发明授权

US09583487B2 Semiconductor device having metallic source and drain regions 有权
标题翻译：具有金属源极和漏极区域的半导体器件
公开(公告)号：US09583487B2
公开(公告)日：2017-02-28
申请号：US13995419
申请日：2011-12-19
申请人： Martin D. Giles , Annalisa Cappellani , Sanaz Kabehie , Rafael Rios , Cory E. Weber , Aaron A. Budrevich
发明人： Martin D. Giles , Annalisa Cappellani , Sanaz Kabehie , Rafael Rios , Cory E. Weber , Aaron A. Budrevich
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/78 , H01L27/092 , H01L27/088 , H01L29/06
CPC分类号： H01L29/7848 , H01L21/2225 , H01L21/2254 , H01L21/2257 , H01L21/2258 , H01L21/28518 , H01L21/28556 , H01L21/28593 , H01L21/30608 , H01L21/30617 , H01L21/3065 , H01L21/823814 , H01L21/823821 , H01L27/088 , H01L27/092 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/401 , H01L29/456 , H01L29/66636 , H01L29/66795 , H01L29/7839 , H01L29/7845 , H01L29/785 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
摘要翻译：描述具有金属源极和漏极区域的半导体器件。例如，半导体器件包括设置在衬底的半导体沟道区域上方的栅电极堆叠。金属源区和漏区设置在衬底的上方，位于半导体沟道区的任一侧。金属源极和漏极区域中的每个具有轮廓。第一半导体外扩散区域设置在衬底中，在半导体沟道区域和金属源极区域之间，并与金属源极区域的形状保持一致。第二半导体外扩散区域设置在衬底中，在半导体沟道区域和金属漏极区域之间，并与金属漏极区域的轮廓保形。

43. 发明授权

US09362074B2 Nanowire-based mechanical switching device 有权
标题翻译：基于纳米线的机械开关装置
公开(公告)号：US09362074B2
公开(公告)日：2016-06-07
申请号：US13996507
申请日：2013-03-14
申请人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
发明人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
IPC分类号： H01H51/22 , H01H59/00 , B82Y10/00 , H01H1/00 , H01H9/02
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

44. 发明申请

US20090020792A1 ISOLATED TRI-GATE TRANSISTOR FABRICATED ON BULK SUBSTRATE 审中-公开
标题翻译：隔离三极晶体管在大块基板上制作
公开(公告)号：US20090020792A1
公开(公告)日：2009-01-22
申请号：US11779284
申请日：2007-07-18
申请人： Rafael Rios , Jack Kavalieros , Stephen M. Cea
发明人： Rafael Rios , Jack Kavalieros , Stephen M. Cea
IPC分类号： H01L29/78 , H01L21/02
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.
摘要翻译：形成隔离的三栅极半导体器件的方法包括：图案化块状衬底以形成翅片结构，在鳍结构周围沉积绝缘材料，使绝缘材料凹陷以暴露将用于三极管的鳍结构的一部分 - 半导体本体，在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，以及执行热氧化工艺以将所述鳍状结构的未受保护的部分氧化在所述氮化物帽下方。翅片的氧化部分隔离被氮化物盖保护的半导体主体。然后可以去除氮化物盖。热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时的时间。

45. 发明授权

US06489655B2 Integrated circuit with dynamic threshold voltage 有权
标题翻译：具有动态阈值电压的集成电路
公开(公告)号：US06489655B2
公开(公告)日：2002-12-03
申请号：US09782540
申请日：2001-02-12
申请人： Brian S. Doyle , Brian Roberds , Rafael Rios
发明人： Brian S. Doyle , Brian Roberds , Rafael Rios
IPC分类号： H01L2701
CPC分类号： H01L29/78621 , H01L29/78606 , H01L29/78696
摘要： An integrated circuit and method for making it are described. The integrated circuit includes a first insulating layer formed on a substrate and a body strap of a first conductivity type that is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer adjacent to the body strap and a film is formed on the second insulating layer. The integrated circuit also includes a gate electrode formed on the film. A plurality of doped regions of a second conductivity type are formed within the film that extend from the surface of the film to the surface of the second insulating layer. The doped regions have junctions that are each spaced from the body strap by at least about 500 angstroms.
摘要翻译：对集成电路及其制作方法进行说明。集成电路包括形成在基板上的第一绝缘层和形成在第一绝缘层上的第一导电类型的主体带。在与体带相邻的第一绝缘层上形成第二绝缘层，并且在第二绝缘层上形成膜。集成电路还包括形成在膜上的栅电极。在薄膜内形成多个第二导电类型的掺杂区，从薄膜的表面延伸到第二绝缘层的表面。掺杂区域具有与体带相隔至少约500埃的交点。

46. 发明申请

US20140035059A1 SEMICONDUCTOR DEVICE HAVING METALLIC SOURCE AND DRAIN REGIONS 有权
标题翻译：具有金属源和漏区的半导体器件
公开(公告)号：US20140035059A1
公开(公告)日：2014-02-06
申请号：US13995419
申请日：2011-12-19
申请人： Martin D. Giles , Annalisa Cappellani , Sanaz Kabehie , Rafael Rios , Cory E. Weber , Aaron A. Budrevich
发明人： Martin D. Giles , Annalisa Cappellani , Sanaz Kabehie , Rafael Rios , Cory E. Weber , Aaron A. Budrevich
IPC分类号： H01L27/092 , H01L21/8238 , H01L27/088
CPC分类号： H01L29/7848 , H01L21/2225 , H01L21/2254 , H01L21/2257 , H01L21/2258 , H01L21/28518 , H01L21/28556 , H01L21/28593 , H01L21/30608 , H01L21/30617 , H01L21/3065 , H01L21/823814 , H01L21/823821 , H01L27/088 , H01L27/092 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/401 , H01L29/456 , H01L29/66636 , H01L29/66795 , H01L29/7839 , H01L29/7845 , H01L29/785 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
摘要翻译：描述具有金属源极和漏极区域的半导体器件。例如，半导体器件包括设置在衬底的半导体沟道区域上方的栅电极堆叠。金属源区和漏区设置在衬底的上方，位于半导体沟道区的任一侧。金属源极和漏极区域中的每个具有轮廓。第一半导体外扩散区域设置在衬底中，在半导体沟道区域和金属源极区域之间，并与金属源极区域的形状保持一致。第二半导体外扩散区域设置在衬底中，在半导体沟道区域和金属漏极区域之间，并与金属漏极区域的轮廓保形。

47. 发明申请

US20080237719A1 Multi-gate structure and method of doping same 审中-公开
标题翻译：多栅极结构及掺杂方法
公开(公告)号：US20080237719A1
公开(公告)日：2008-10-02
申请号：US11729198
申请日：2007-03-28
申请人： Brian S. Doyle , Suman Datta , Jack T. Kavalieros , Rafael Rios
发明人： Brian S. Doyle , Suman Datta , Jack T. Kavalieros , Rafael Rios
IPC分类号： H01L27/12 , H01L21/8238
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/66803
摘要： A multi-gate structure includes a substrate (110, 210, 410), an electrically insulating layer (120, 220, 420) over the substrate, and a first semiconducting fin (130, 230, 430) above the electrically insulating layer. The first semiconducting fin includes a top region (131, 231, 431), a first side region (132, 232, 432), and a second side region (133, 233, 433). The top region, the first side region, and the second side region have doping concentrations that are substantially equal to each other. The multi-gate structure may be made by depositing a solid source material (510) over the semiconducting fin, and by annealing the multi-gate structure such that dopants from the solid source material diffuse into the semiconducting fin and uniformly dope the top region and the first and second side regions.
摘要翻译：多栅极结构包括衬底（110,210,410），在衬底上方的电绝缘层（120,220,420）以及在电绝缘层上方的第一半导电翅片（130,230,430）。第一半导体鳍片包括顶部区域（131,231,431），第一侧面区域（132,232,432）和第二侧面区域（133,233,433）。顶部区域，第一侧面区域和第二侧面区域具有彼此基本相等的掺杂浓度。多栅极结构可以通过在半导体鳍上沉积固体源材料（510）并且通过退火多栅极结构使得来自固体源材料的掺杂剂扩散到半导体翅片中并且均匀地掺杂顶部区域和第一和第二侧区域。

48. 发明授权

US07091560B2 Method and structure to decrease area capacitance within a buried insulator device 失效
标题翻译：降低埋层绝缘体内部面积电容的方法和结构
公开(公告)号：US07091560B2
公开(公告)日：2006-08-15
申请号：US10806609
申请日：2004-03-22
申请人： Mark A. Stettler , Borna Obradovic , Martin D. Giles , Rafael Rios
发明人： Mark A. Stettler , Borna Obradovic , Martin D. Giles , Rafael Rios
IPC分类号： H01L27/01 , H01L21/336
CPC分类号： B82Y10/00 , H01L29/66772 , H01L29/78603 , H01L29/78606
摘要： Method and structure to decrease area capacitance within a buried insulator device structure are disclosed. A portion of the substrate layer of a buried insulator structure opposite the insulator layer from the gate is doped with the same doping polarity as the source and drain regions of the device, to provide reduced area capacitance. Such doping may be limited to portions of the substrate which are not below the gate.
摘要翻译：公开了减少掩埋绝缘体器件结构内的面积电容的方法和结构。与栅极的绝缘体层相对的掩埋绝缘体结构的衬底层的一部分掺杂有与器件的源极和漏极区相同的掺杂极性，以提供减小的面积电容。这种掺杂可以限于不在栅极下方的衬底的部分。

49. 发明申请

US20060046452A1 N-gate transistor 审中-公开
标题翻译： N栅晶体管
公开(公告)号：US20060046452A1
公开(公告)日：2006-03-02
申请号：US11208159
申请日：2005-08-19
申请人： Rafael Rios , Brian Doyle , Thomas Linton , Jack Kavalieros
发明人： Rafael Rios , Brian Doyle , Thomas Linton , Jack Kavalieros
IPC分类号： H01L21/3205
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A n-gate transistor, and method of forming such, including source/drain regions connected by a channel region and a gate electrode coupled to the channel region. The channel region has many angled edges protruding into the gate electrode. The many angled edges are to act as electrically conducting channel conduits between source/drain regions.
摘要翻译：一种n型栅极晶体管及其形成方法，包括由沟道区域连接的源极/漏极区域和耦合到沟道区域的栅电极。通道区域具有突出到栅电极中的许多成角度的边缘。许多成角度的边缘用作在源极/漏极区域之间的导电沟道导管。

50. 发明授权

US06960517B2 N-gate transistor 失效
标题翻译： N栅晶体管
公开(公告)号：US06960517B2
公开(公告)日：2005-11-01
申请号：US10610835
申请日：2003-06-30
申请人： Rafael Rios , Brian S. Doyle , Thomas D. Linton, Jr. , Jack Kavalieros
发明人： Rafael Rios , Brian S. Doyle , Thomas D. Linton, Jr. , Jack Kavalieros
IPC分类号： H01L21/336 , H01L29/786 , H01L21/3205
CPC分类号： H01L29/7853 , H01L29/66795
摘要： A n-gate transistor, and method of forming such, including source/drain regions connected by a channel region and a gate electrode coupled to the channel region. The channel region has many angled edges protruding into the gate electrode. The many angled edges are to act as electrically conducting channel conduits between source/drain regions.
摘要翻译：一种n型栅极晶体管及其形成方法，包括由沟道区域连接的源极/漏极区域和耦合到沟道区域的栅电极。通道区域具有突出到栅电极中的许多成角度的边缘。许多成角度的边缘用作在源极/漏极区域之间的导电沟道导管。

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