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11. 发明申请

US20080307240A1 POWER MANAGEMENT ELECTRONIC CIRCUITS, SYSTEMS, AND METHODS AND PROCESSES OF MANUFACTURE 审中-公开
标题翻译：电力管理电子电路，系统及其制造方法和工艺
公开(公告)号：US20080307240A1
公开(公告)日：2008-12-11
申请号：US11760263
申请日：2007-06-08
申请人： Franck Dahan , Gilles Dubost , Gordon Gammie , Uming Ko , Hugh Mair , Sang-Won Song , Alice Wang , William D. Wilson
发明人： Franck Dahan , Gilles Dubost , Gordon Gammie , Uming Ko , Hugh Mair , Sang-Won Song , Alice Wang , William D. Wilson
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/06 , G06F1/08 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F21/79 , Y02D10/126 , Y02D10/128 , Y02D10/172 , Y02D50/20
摘要： An electronic circuit including a power managed circuit (2610), and a power management control circuit (3570) coupled to the power managed circuit (2610) and operable to select between at least a first operating performance point (OPP1) and a second higher operating performance point (OPP2) for the power managed circuit (2610), each performance point including a respective pair (Vn, Fn) of voltage and operating frequency, and the power management control circuit (3570) further operable to control dynamic power switching of the power managed circuit (2610) based on a condition wherein the power managed circuit (2610) at a given operating performance point has a static power dissipation (4820.1), and the dynamic power switching puts the power managed circuit in a lower static power state (4860.1) that dissipates less power than the static power dissipation (4820.1).
摘要翻译：一种电子电路，包括功率管理电路（2610）和耦合到功率管理电路（2610）的功率管理控制电路（3570），并且可操作以在至少第一操作性能点（OPP1）和第二较高操作功率管理电路（2610）的性能点（OPP2），每个性能点包括电压和工作频率的相应对（Vn，Fn），并且功率管理控制电路（3570）还可操作以控制功率管理电路功率管理电路（2610），其中在给定操作性能点处的功率管理电路（2610）具有静态功耗（4820.1），并且动态功率开关将功率管理电路置于较低的静态功率状态 4860.1），功耗比静态功耗（4820.1）要低。

12. 发明授权

US08278980B1 Enhancement of power management using dynamic voltage and frequency scaling and digital phase lock loop high speed bypass mode 有权
公开(公告)号：US08278980B1
公开(公告)日：2012-10-02
申请号：US13484472
申请日：2012-05-31
申请人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
发明人： Gilles Dubost , Franck Dahan , Hugh Thomas Mair , Sylvain Dubois
IPC分类号： H03L7/06
CPC分类号： H03L7/0805 , H03L7/0812 , H03L7/22
摘要： An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.

13. 发明申请

US20080162980A1 Memory Controller Idle Mode 有权
标题翻译：内存控制器空闲模式
公开(公告)号：US20080162980A1
公开(公告)日：2008-07-03
申请号：US11948844
申请日：2007-11-30
申请人： Franck Dahan , Gilles Dubost , Sylvain Dubois
发明人： Franck Dahan , Gilles Dubost , Sylvain Dubois
IPC分类号： G06F5/06 , G06F12/00
CPC分类号： G06F13/1694 , Y02D10/14
摘要： An apparatus and method for dynamically modifying one or more operating conditions of a memory controller in an electronic device. Operating conditions may comprise clock frequency and power, which may be modified or removed. Dynamic modification of operating conditions may be done for purposes of optimizing a parameter, such as power consumption. A mode, referred to as idle mode, may be used as a transitional or operational mode for the memory controller. The performance of the memory controller may dynamically vary in response to changes in its operating conditions. As such, the memory controller may comprise multiple modes, or submodes, of operation. The performance of the memory controller may depend on the type of memory it controls, for instance Double Data Rate (DDR) Dynamic Random Access Memory (DRAM).
摘要翻译：一种用于动态修改电子设备中的存储器控制器的一个或多个操作条件的装置和方法。操作条件可以包括时钟频率和功率，其可以被修改或去除。操作条件的动态修改可以用于优化诸如功率消耗之类的参数的目的。称为空闲模式的模式可以用作存储器控制器的过渡或操作模式。存储器控制器的性能可以根据其操作条件的变化而动态变化。因此，存储器控制器可以包括操作的多种模式或子模式。存储器控制器的性能可以取决于其控制的存储器的类型，例如双数据速率（DDR）动态随机存取存储器（DRAM）。

14. 发明授权

US08812885B2 Detecting wake-up events for a chip based on an I/O power supply 有权
标题翻译：基于I / O电源检测芯片的唤醒事件
公开(公告)号：US08812885B2
公开(公告)日：2014-08-19
申请号：US11695304
申请日：2007-04-02
申请人： Philippe Royannez , Gilles Dubost , Christophe Vatinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
发明人： Philippe Royannez , Gilles Dubost , Christophe Vatinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
摘要翻译：提供了一种包括具有处理器和唤醒逻辑的芯片的设备。该装置还包括耦合到芯片的电源管理电路。电源管理电路选择性地向芯片提供核心电源和输入/输出（I / O）电源。即使电源管理电路切断芯片的核心电源，唤醒逻辑也会根据I / O电源提供的电源来检测和响应唤醒事件。

15. 发明申请

US20080162969A1 DETECTING WAKE-UP EVENTS FOR A CHIP BASED ON AN I/O POWER SUPPLY 有权
标题翻译：检测基于I / O电源的芯片的唤醒事件
公开(公告)号：US20080162969A1
公开(公告)日：2008-07-03
申请号：US11695304
申请日：2007-04-02
申请人： Philippe Royannez , Gilles Dubost , Christophe Vantinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
发明人： Philippe Royannez , Gilles Dubost , Christophe Vantinel , William Douglas Wilson , Vinod Menezes , Hugh Mair , James Sangwon Song
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A device is provided that includes a chip having a processor and wake-up logic. The device also includes power management circuitry coupled to the chip. The power management circuitry selectively provides a core power supply and an input/output (I/O) power supply to the chip. Even if the power management circuitry cuts off the core power supply to the chip, the wake-up logic detects and responds to wake-up events based on power provided by the I/O power supply.
摘要翻译：提供了一种包括具有处理器和唤醒逻辑的芯片的设备。该装置还包括耦合到芯片的电源管理电路。电源管理电路选择性地向芯片提供核心电源和输入/输出（I / O）电源。即使电源管理电路切断芯片的核心电源，唤醒逻辑也会根据I / O电源提供的电源来检测和响应唤醒事件。

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