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21. 发明授权

US5886942A Word line driver and semiconductor device 失效
标题翻译：字线驱动器和半导体器件
公开(公告)号：US5886942A
公开(公告)日：1999-03-23
申请号：US964398
申请日：1997-11-06
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： G11C11/407 , G11C8/08 , G11C11/408 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： A word line driver includes a CMOS inverter constituted by a P channel MOS transistor in which a row decode signal having the amplitude of an internal logic power supply voltage is supplied to a gate, one end of the source-drain current path is connected to a node to which a power supply voltage (VWLh) is applied, and the other end of the source-drain current path is connected to a word line, and an N channel MOS transistor in which the input signal is supplied to a gate, one end of the source-drain current path is connected to a node to which a power supply voltage (VWLl) having a negative value is applied, and the other end of the source-drain current path is connected to the word line. The circuit threshold voltage of the CMOS inverter is set to be larger than the circuit threshold voltages of other CMOS inverters which operate using internal logic power supply voltages.
摘要翻译：字线驱动器包括由P沟道MOS晶体管构成的CMOS反相器，其中具有内部逻辑电源电压的幅度的行解码信号被提供给栅极，源极 - 漏极电流路径的一端连接到施加电源电压（VWLh）的节点，源极 - 漏极电流路径的另一端连接到字线，并且其中输入信号被提供给栅极的N沟道MOS晶体管，一端源极 - 漏极电流路径连接到其上施加了负值的电源电压（VWL1）的节点，并且源极 - 漏极电流路径的另一端连接到字线。将CMOS反相器的电路阈值电压设置为大于使用内部逻辑电源电压工作的其他CMOS反相器的电路阈值电压。

22. 发明授权

US09991912B2 Transmitting device, receiving device and transmitting/receiving system 有权
公开(公告)号：US09991912B2
公开(公告)日：2018-06-05
申请号：US13519804
申请日：2011-06-02
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： H04L7/04 , H04B1/04 , H04L7/00 , H04L7/033 , H04B15/02 , H04B15/04
CPC分类号： H04B1/0475 , H04B15/04 , H04B15/06 , H04L7/0008 , H04L7/0337
摘要： A transmitting device has a transmission data generating part and an output buffer part. The transmission data generating part transmits a data and a clock, which are to be transmitted to a receiving device, and outputs them to the output buffer part. The output buffer part includes a data transmitting part and a clock transmitting part. The clock transmitting part generates and transmits a clock intermittently phase-shifted. The data transmitting part transmits the data in sync with the clock transmitted from the clock transmitting part.

23. 发明授权

US09019259B2 Transmission apparatus, reception apparatus, transmission-reception system, and image display system 有权
标题翻译：发送装置，接收装置，发送接收系统和图像显示系统
公开(公告)号：US09019259B2
公开(公告)日：2015-04-28
申请号：US13265083
申请日：2010-04-22
申请人： Seiichi Ozawa , Hironobu Akita
发明人： Seiichi Ozawa , Hironobu Akita
IPC分类号： G09G5/00 , H04L7/00 , G09G3/36 , H04N5/66 , H04N5/12
CPC分类号： H04L7/0008 , G09G3/3611 , G09G2310/08 , G09G2370/08 , H04L7/0091 , H04N5/12 , H04N5/66
摘要： The present invention provides a transmission apparatus and a reception apparatus easy to sample data correctly by a clock in the reception apparatus. In a detection section 25 of a reception apparatus 20n, based on data output from a sampler section 23, both or either of detection of a phase difference between data received by a data reception section 21 and a clock received by a clock reception section 22, and/or waveform distortion of this data is performed. A detection signal indicating a result of detection by the detection section 25 is transmitted to a transmission apparatus 10 by a detection signal transmission section 26. In the transmission apparatus 10, by a control section 15, based on the detection signal received by a detection signal reception section 14, both or either of control of adjustment of a phase between data transmitted by a data transmission section 11 and a clock transmitted by a clock transmission section 12, and/or adjustment of an amplitude of the data is performed.
摘要翻译：本发明提供一种易于通过接收装置中的时钟对数据进行正确采样的发送装置和接收装置。在接收装置20n的检测部25中，根据从取样部23输出的数据，检测由数据接收部21接收到的数据与时钟接收部22接收的时钟之间的相位差，和/或该数据的波形失真。表示检测部25的检测结果的检测信号由检测信号发送部26发送到发送装置10.在发送装置10中，通过控制部15，基于由检测信号接收部14，执行由数据发送部11发送的数据与时钟发送部12发送的时钟之间的相位的调整的控制和/或数据的振幅的调整。

24. 发明申请

US20120321002A1 TRANSMITTING DEVICE, RECEIVING DEVICE AND TRANSMITTING/RECEIVING SYSTEM 有权
标题翻译：发送设备，接收设备和发送/接收系统
公开(公告)号：US20120321002A1
公开(公告)日：2012-12-20
申请号：US13519804
申请日：2011-06-02
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： H04L27/00
CPC分类号： H04B1/0475 , H04B15/04 , H04B15/06 , H04L7/0008 , H04L7/0337
摘要： A transmitting device 10A has a transmission data generating part 11 and an output buffer part 12A. The transmission data generating part 11 transmits a data 1 and a clock 1, which are to be transmitted to a receiving device, and outputs them to the output buffer part 12A. The output buffer part 12A includes a data transmitting part 13 and a clock transmitting part 14A. The clock transmitting part 14A generates and transmits a clock intermittently phase-shifted. The data transmitting part 13 transmits the data in sync with the clock transmitted from the clock transmitting part 14A.
摘要翻译：发送装置10A具有发送数据生成部11和输出缓冲部12A。发送数据生成部11发送要发送到接收装置的数据1和时钟1，并将其输出到输出缓冲器部分12A。输出缓冲器部分12A包括数据发送部分13和时钟发送部分14A。时钟发送部14A生成并发送间歇地相移的时钟。数据发送部13与从时钟发送部14A发送的时钟同步发送数据。

25. 发明申请

US20110057690A1 CLOCK CONTROL CIRCUIT AND TRANSMITTER 有权
标题翻译：时钟控制电路和发射机
公开(公告)号：US20110057690A1
公开(公告)日：2011-03-10
申请号：US12747807
申请日：2009-12-09
申请人： Hironobu Akita
发明人： Hironobu Akita
IPC分类号： H03L7/00
CPC分类号： H04B15/04 , H04B2215/067
摘要： A transmitter 1 comprises a clock generation portion 4, FIFO portion 6, and serial signal creation portion 7. The clock generation portion 4 performs modulation by spectrum spreading of a reference clock CKref, and generates a first clock CK1 with a high modulation factor and a second clock CK2 with a low modulation factor. The FIFO portion 6 takes as inputs the first clock CK1 which has been output from the clock generation portion 4 to a data generation portion 2 and output from the data generation portion 2, a parallel data signal which has been synchronized with the first clock CK1 in the data generation portion 2 and output, and the second clock CK2 output from the clock generation portion 4, and synchronizes the parallel data signal Pdata with the second clock CK2 and outputs the parallel data signal Pdata. The serial signal creation portion 7 converts a parallel data signal PRdata into a serial data signal Sdata.
摘要翻译：发射机1包括时钟产生部分4，FIFO部分6和串行信号产生部分7.时钟产生部分4通过参考时钟CKref的频谱扩展执行调制，并产生具有高调制因数的第一时钟CK1和具有低调制因子的第二时钟CK2。 FIFO部分6将已经从时钟产生部分4输出的第一时钟CK1作为输入，作为数据生成部分2输出，并从数据生成部分2输出与第一时钟CK1同步的并行数据信号数据产生部分2和从时钟产生部分4输出的第二时钟CK2，并行并行数据信号Pdata与第二时钟CK2并输出并行数据信号Pdata。串行信号产生部分7将并行数据信号PRdata转换为串行数据信号Sdata。

26. 发明授权

US06433619B1 Pump circuit boosting a supply voltage 有权
公开(公告)号：US06433619B1
公开(公告)日：2002-08-13
申请号：US09972905
申请日：2001-10-10
申请人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
发明人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
IPC分类号： G05F110
摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.

27. 发明授权

US06313674B1 Synchronizing circuit for generating internal signal synchronized to external signal 有权
标题翻译：同步电路，用于产生与外部信号同步的内部信号
公开(公告)号：US06313674B1
公开(公告)日：2001-11-06
申请号：US09641139
申请日：2000-08-16
申请人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe
发明人： Hironobu Akita , Satoshi Eto , Katsuaki Isobe
IPC分类号： H03L706
CPC分类号： G11C7/222 , G06F1/10 , G11C7/22 , H03K5/135 , H03L7/0812
摘要： A variable delay line outputs a clock signal advanced in phase by a time corresponding to a sum tH+tL of a time tH required to output high level data from an OCD circuit and a time tL required to output low level data from the OCD circuit. A replica circuit for outputting low level data has the same configuration as a circuit portion of the OCD circuit through which low level data passes. The replica circuit outputs a start signal SSH for outputting high level data from the OCD circuit. Another replica circuit for outputting high level data has the same configuration as a circuit portion of the OCD circuit through which high level data passes. The replica circuit outputs a start signal SSL for outputting low level data from the OCD circuit.
摘要翻译：可变延迟线输出相位提前的时钟信号与从OCD电路输出高电平数据所需的时间tH的和tH + tL和从OCD电路输出低电平数据所需的时间tL的时间。用于输出低电平数据的复制电路具有与低电平数据通过的OCD电路的电路部分相同的配置。复制电路输出用于从OCD电路输出高电平数据的启动信号SSH。用于输出高电平数据的另一复制电路具有与高电平数据通过的OCD电路的电路部分相同的配置。复制电路输出用于从OCD电路输出低电平数据的起始信号SSL。

28. 发明授权

US06212090B1 Semiconductor device including a repetitive pattern 失效
公开(公告)号：US06212090B1
公开(公告)日：2001-04-03
申请号：US09471038
申请日：1999-12-23
申请人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
发明人： Hironobu Akita , Shinichiro Shiratake , Fumihiro Kohno
IPC分类号： G11C506
CPC分类号： G11C8/10 , G11C8/14 , G11C11/4087 , H01L27/10897
摘要： The present invention provides a DRAM in which a first repetitive unit including a plurality of decoders for selecting a plurality of word lines and a second repetitive unit having the same arrangement as that of the first repetitive unit are arranged symmetrically with respect a boundary region therebetween. The first and second repetitive units have a wire and a contact located on a boundary portion therebetween in common.

29. 发明授权

US6144599A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6144599A
公开(公告)日：2000-11-07
申请号：US191414
申请日：1998-11-12
申请人： Hironobu Akita , Kenji Tsuchida
发明人： Hironobu Akita , Kenji Tsuchida
IPC分类号： G11C11/409 , G11C7/06 , G11C7/12 , G11C11/401 , G11C11/4091 , G11C11/4094 , G11C29/00 , G11C29/04 , G11C11/419
CPC分类号： G11C7/06 , G11C11/4091 , G11C11/4094 , G11C7/12 , G11C29/83
摘要： In a DRAM semiconductor device comprising a bit line equalizer for setting a potential on paired bit lines to a potential on a precharge power source line, a sense amplifier circuit amplifying a potential difference across the paired bit lines and detecting data, sense amplifier drive lines, for applying a sense amplifier drive signal for driving the sense amplifier circuit to the sense amplifier circuit, and a sense amplifier/drive line equalizer, a current limiter element is so provided that, between a precharge power source line and the sense amplifier drive line, it is connected in series with the current path of the equalizer. By so providing the current limiter element, it is possible to, even if there occurs any cross-fail between the bit line and the word line, reduce a short-circuiting current at a precharging time or prevent generation of the short-circuiting current.
摘要翻译：在包括用于将成对位线上的电位设置为预充电电源线上的电位的位线均衡器的DRAM半导体器件中，放大成对位线之间的电位差和检测数据，读出放大器驱动线的读出放大器电路，为了将读出放大器驱动信号用于驱动读出放大器电路到读出放大器电路，以及读出放大器/驱动线均衡器，限流元件被设置成在预充电电源线和读出放大器驱动线之间，它与均衡器的当前路径串联连接。通过提供电流限制器元件，即使在位线和字线之间发生任何交叉故障，也可以在预充电时间减少短路电流或者防止短路电流的产生。

30. 发明授权

US08363771B2 Transmission device, receiving device and communication system 有权
标题翻译：传输设备，接收设备和通信系统
公开(公告)号：US08363771B2
公开(公告)日：2013-01-29
申请号：US12808598
申请日：2009-10-27
申请人： Hironobu Akita , Seiichi Ozawa , Yohei Ishizone , Satoshi Miura
发明人： Hironobu Akita , Seiichi Ozawa , Yohei Ishizone , Satoshi Miura
IPC分类号： H04L7/04
CPC分类号： H04L7/10 , G09G5/008 , H03L7/095 , H04L7/033 , H04L7/046
摘要： Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.
摘要翻译：提供具有简单配置并能够可靠地执行改变的比特率的确认的传输设备，接收设备和通信系统。通信系统1向发送装置3发送串行数据信号Sdata，该串行数据信号Sdata在传输中的串行数据信号Sdata的比特率时，在时钟周期的恒定倍数的周期内被设置为恒定值设备2更改。接收到串行数据信号Sdata的接收装置3当确定串行数据信号Sdata在时钟的周期的恒定倍数的周期内是恒定值时，从发送装置2接收训练数据Tdata，并且进行以确认改变的比特率的处理。

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