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41. 发明授权

US08984041B2 Performing arithmetic operations using both large and small floating point values 有权
标题翻译：使用大和小浮点值执行算术运算
公开(公告)号：US08984041B2
公开(公告)日：2015-03-17
申请号：US13598847
申请日：2012-08-30
申请人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
发明人： John B. Carter , Bruce G. Mealey , Karthick Rajamani , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F7/38 , G06F7/483
CPC分类号： G06F7/483 , G06F2207/382
摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.
摘要翻译：提供了用于在数据处理系统中执行浮点算术运算的机构。接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值，至少一个浮点操作数的尾数的位的范围。基于向量值和多个浮点操作数，生成用于浮点运算的结果值。

42. 发明申请

US20130117513A1 MEMORY QUEUE HANDLING TECHNIQUES FOR REDUCING IMPACT OF HIGH LATENCY MEMORY OPERATIONS 有权
标题翻译：用于减少高级存储器操作影响的存储器队列处理技术
公开(公告)号：US20130117513A1
公开(公告)日：2013-05-09
申请号：US13290702
申请日：2011-11-07
申请人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Mark A. Brittain , John Steven Dodson , Benjiman L. Goodman , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/14
CPC分类号： G06F13/1626 , G06F13/16
摘要： Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations.
摘要翻译：用于处理存储器访问排队的技术防止传递过多的请求，这些请求涉及存储器的区域，这些存储器受到诸如存储器刷新操作，存储器擦除或内部总线校准事件的高等待时间存储器操作到存储器的重新排序队列控制器。存储器控制器包括用于存储未决存储器访问请求的队列，用于接收请求的重新排序队列，以及实现队列控制器的控制逻辑，该队列控制器确定接收到的请求和正在进行的高延迟存储器操作之间是否存在冲突。如果存在冲突，则将请求转发到重新排序队列可能被直接拒绝，或者可能使用与高等待时间操作相冲突的现有排队操作的计数来确定新请求的队列是否将超过阈值此类操作的数量。

43. 发明授权

US08139430B2 Power-on initialization and test for a cascade interconnect memory system 失效
标题翻译：级联互连存储器系统的上电初始化和测试
公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G11C7/10 , G11C7/18
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

44. 发明授权

US08122223B2 Access speculation predictor with predictions based on memory region prior requestor tag information 有权
标题翻译：基于存储区域先前请求者标签信息的预测访问推测预测器
公开(公告)号：US08122223B2
公开(公告)日：2012-02-21
申请号：US12105401
申请日：2008-04-18
申请人： Jason F. Cantin , Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Jason F. Cantin , Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/1016 , Y02D10/13
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester tag may be extracted from a first data request and a finite state machine (FSM) of a memory controller may be selected whose memory region includes the first address. A second requester tag, that identifies a previous requester that attempted to access the memory region association with the selected FSM, may be retrieved from a register associated with the selected FSM and compared to the first requester tag. Speculatively retrieving the data for the first data request from a main memory may be controlled based on results of the comparison of the first requester tag to the second requester tag.
摘要翻译：访问推测预测器可以基于当前请求者标签是否匹配先前的请求者标签来预测是否对来自主存储器的数据请求的数据进行推测检索。特别地，可以从第一数据请求中提取第一地址和第一请求者标签，并且可以选择存储器控制器的有限状态机（FSM），其存储器区域包括第一地址。可以从与所选FSM相关联的寄存器中检索识别尝试访问与选择的FSM的存储器区域关联的先前请求者的第二请求者标签，并与第一请求者标签进行比较。可以基于第一请求者标签与第二请求者标签的比较的结果来控制从主存储器推测地检索第一数据请求的数据。

45. 发明申请

US20090327619A1 Access Speculation Predictor with Predictions Based on Memory Region Prior Requestor Tag Information 有权
标题翻译：基于内存区域预先请求者标签信息的预测访问推测预测器
公开(公告)号：US20090327619A1
公开(公告)日：2009-12-31
申请号：US12105401
申请日：2008-04-18
申请人： Jason F. Cantin , Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Jason F. Cantin , Richard Nicholas , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/1016 , Y02D10/13
摘要： An access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory based on whether or not a current requestor tag matches a previous requestor tag. In particular, a first address and a first requester tag may be extracted from a first data request and a finite state machine (FSM) of a memory controller may be selected whose memory region includes the first address. A second requester tag, that identifies a previous requester that attempted to access the memory region association with the selected FSM, may be retrieved from a register associated with the selected FSM and compared to the first requester tag. Speculatively retrieving the data for the first data request from a main memory may be controlled based on results of the comparison of the first requester tag to the second requester tag.
摘要翻译：访问推测预测器可以基于当前请求者标签是否匹配先前的请求者标签来预测是否对来自主存储器的数据请求的数据进行推测检索。特别地，可以从第一数据请求中提取第一地址和第一请求者标签，并且可以选择存储器控制器的有限状态机（FSM），其存储器区域包括第一地址。可以从与所选FSM相关联的寄存器中检索识别尝试访问与选择的FSM的存储器区域关联的先前请求者的第二请求者标签，并与第一请求者标签进行比较。可以基于第一请求者标签与第二请求者标签的比较的结果来控制从主存储器推测地检索第一数据请求的数据。

46. 发明申请

US20090265293A1 Access speculation predictor implemented via idle command processing resources 失效
标题翻译：通过空闲命令处理资源实现访问推测预测器
公开(公告)号：US20090265293A1
公开(公告)日：2009-10-22
申请号：US12105427
申请日：2008-04-18
申请人： Richard Nicholas , Ram Raghavan , Eric E. Retter , Jeffrey A. Stuecheli
发明人： Richard Nicholas , Ram Raghavan , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06N5/00
CPC分类号： G06F12/0862 , G06F12/0831 , G06F2212/507 , G06F2212/6022 , G06F2212/6024 , Y02D10/13
摘要： An access speculation predictor is provided that may be implemented using idle command processing resources, such as registers of idle finite state machines (FSMs) in a memory controller. The access speculation predictor may predict whether to perform speculative retrieval of data for a data request from a main memory of the data processing system based on history information stored for a memory region targeted by the data request. In particular, a first address may be extracted from the data request and compared to memory regions associated with second addresses stored in address registers of a plurality of FSMs of the memory controller. A FSM whose memory region includes the first address may be selected. History information for the memory region may be obtained from the selected FSM. The history information may be used to control whether to speculatively retrieve the data for the data request from a main memory.
摘要翻译：提供了可以使用诸如存储器控制器中的空闲有限状态机（FSM）的寄存器的空闲命令处理资源来实现的访问推测预测器。访问推测预测器可以基于针对数据请求所针对的存储区域存储的历史信息来预测是否对数据处理系统的主存储器执行针对数据请求的数据的推测检索。特别地，可以从数据请求中提取第一地址，并与存储在存储器控制器的多个FSM的地址寄存器中的第二地址相关联的存储器区域进行比较。可以选择其存储区域包括第一地址的FSM。可以从所选择的FSM获得用于存储器区域的历史信息。历史信息可以用于控制是否从主存储器推测性地检索数据请求的数据。

47. 发明申请

US20080126911A1 MEMORY WRAP TEST MODE USING FUNCTIONAL READ/WRITE BUFFERS 失效
标题翻译：使用功能读/写缓冲存储器封装测试模式
公开(公告)号：US20080126911A1
公开(公告)日：2008-05-29
申请号：US11466111
申请日：2006-08-22
申请人： Mark A. Brittain , Edgar R. Cordero , John T. Hollaway , Eric E. Retter
发明人： Mark A. Brittain , Edgar R. Cordero , John T. Hollaway , Eric E. Retter
IPC分类号： G11C29/00
CPC分类号： G01R31/31722 , G01R31/31712 , G11C29/48
摘要： A memory controller for a processing unit provides a memory wrap test mode path which selectively writes data from the write buffer of the controller to the read buffer of the controller, thereby allowing the write and read buffers to substitute for a system memory device during testing of the processing unit. The processing unit can thus be tested without the attached memory device yet still operate under conditions which generate bus traffic and chip noise similar to that generated under actual (end-use) operation. When a processor issues a write operation in test mode, the controller writes the data to an entry of the read buffer which corresponds to the write address. Thereafter, the processor can issue a read operation with the same address and the read buffer will send the data from the corresponding entry.
摘要翻译：用于处理单元的存储器控制器提供存储器包裹测试模式路径，其选择性地将数据从控制器的写入缓冲器写入到控制器的读取缓冲器，从而允许写入和读取缓冲器在测试期间替换系统存储器件处理单元。因此，处理单元可以在没有附加的存储器件的情况下进行测试，但仍然在产生与实际（最终使用）操作下生成的总线流量和芯片噪声类似的条件下操作。当处理器在测试模式下发出写入操作时，控制器将数据写入对应于写入地址的读取缓冲器的条目。此后，处理器可以发出具有相同地址的读取操作，并且读取缓冲器将从相应的条目发送数据。

48. 发明申请

US20080040563A1 SYSTEMS AND METHODS FOR MEMORY MODULE POWER MANAGEMENT 失效
标题翻译：用于存储器模块电源管理的系统和方法
公开(公告)号：US20080040563A1
公开(公告)日：2008-02-14
申请号：US11463743
申请日：2006-08-10
申请人： Mark A. Brittain , Warren E. Maule , Karthick Rajamani , Eric E. Retter , Robert B. Tremaine
发明人： Mark A. Brittain , Warren E. Maule , Karthick Rajamani , Eric E. Retter , Robert B. Tremaine
IPC分类号： G06F13/00 , G06F1/32
CPC分类号： G11C5/143 , G06F1/3225 , G11C5/04 , G11C5/14 , G11C11/4072
摘要： Systems and methods for determining memory module power requirements in a memory system. Embodiments include a memory system with a physical memory and a memory controller. The physical memory includes a plurality of memory devices. The memory controller is in communication with the physical memory and has a logical memory for storing power usage characteristics associated with the physical memory. The power usage characteristics are generated in response to a current operating environment of the memory system.
摘要翻译：用于确定存储器系统中的存储器模块功率需求的系统和方法。实施例包括具有物理存储器和存储器控制器的存储器系统。物理存储器包括多个存储器件。存储器控制器与物理存储器通信，并且具有用于存储与物理存储器相关联的功率使用特性的逻辑存储器。响应于存储器系统的当前操作环境而产生功率使用特性。

49. 发明授权

US06611159B1 Apparatus and method for synchronizing multiple circuits clocked at a divided phase locked loop frequency 失效
标题翻译：用于同步以分频锁相环频率计时的多个电路的装置和方法
公开(公告)号：US06611159B1
公开(公告)日：2003-08-26
申请号：US10078224
申请日：2002-02-19
申请人： Louis C. Milano , Eric E. Retter , Roger S. Rutter , Michael P. Vachon
发明人： Louis C. Milano , Eric E. Retter , Roger S. Rutter , Michael P. Vachon
IPC分类号： H03L706
CPC分类号： G06F1/06 , H03L7/07 , H03L7/095
摘要： An apparatus and method for synchronizing multiple circuits or chips clocked at a divided phase lock loop (PLL) frequency. The apparatus generally includes a plurality of chips, each chip including a phase locked loop (PLL) and a circuit for generating a system clock signal, a circuit for receiving the lock signal from each PLL and for generating an All-Locked signal in response to all of the PLLs achieving lock, and a synchronizing circuit for synchronizing the system clocks of the plurality of chips upon receipt of the All-Locked signal.
摘要翻译：用于同步以分频锁相环（PLL）频率计时的多个电路或芯片的装置和方法。该装置通常包括多个芯片，每个芯片包括锁相环（PLL）和用于产生系统时钟信号的电路，用于从每个PLL接收锁定信号的电路，并响应于实现锁定的所有PLL，以及用于在接收到全锁定信号时同步多个芯片的系统时钟的同步电路。

50. 发明授权

US5625836A SIMD/MIMD processing memory element (PME) 失效
公开(公告)号：US5625836A
公开(公告)日：1997-04-29
申请号：US459374
申请日：1995-06-02
申请人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
发明人： Thomas N. Barker , Clive A. Collins , Michael C. Dapp , James W. Dieffenderfer , Donald M. Lesmeister , Richard E. Nier , Eric E. Retter , Robert R. Richardson , Vincent J. Smoral
IPC分类号： G06F7/57 , G06F9/30 , G06F9/318 , G06F9/38 , G06F15/173 , G06F15/80 , G06F15/16
CPC分类号： G06F15/17337 , G06F15/17343 , G06F15/17368 , G06F15/17381 , G06F15/8007 , G06F15/803 , G06F7/483 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. Significant software flexibility is provided to enable quick implementation of existing programs written in common languages. It is a developable and expandable technology without need to develop new pinouts, new software, or new utilities as chip density increases and new hardware is provided for a chip function. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors, and can be used for lower, intermediate and higher ranges. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer. There is program compatibility for the fully scalable system.

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