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    • 7. 发明授权
    • Semiconductor memory and method for testing the same
    • 半导体存储器及其测试方法
    • US08433960B2
    • 2013-04-30
    • US13279111
    • 2011-10-21
    • Kaoru Mori
    • Kaoru Mori
    • G11C29/00
    • G11C29/16G11C2029/1804
    • A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time. When a CR (configuration register) control circuit detects write commands to write to an address or read commands to read from the address in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command in response to a control signal from the outside. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads.
    • 一种在测试时间内在多个CR中设定任意操作模式信息的半导体存储器。 当CR(配置寄存器)控制电路检测到写入命令以写入地址或读取命令以按预定顺序从地址读取时,CR控制电路在时分上更新多个CR中的每一个的操作模式信息 基础。 命令生成部分响应于来自外部的控制信号生成写命令,读命令或测试开始命令。 数据块压缩电路通过使用输入到数据块的一部分的测试数据,在将测试数据或其原始状态根据代码反转之后,将待写入的操作模式信息改变为用于其余部分的数据 数据垫。
    • 10. 发明授权
    • Semiconductor memory
    • 半导体存储器
    • US07362630B2
    • 2008-04-22
    • US11714766
    • 2007-03-07
    • Kaoru MoriYoshiaki Okuyama
    • Kaoru MoriYoshiaki Okuyama
    • G11C29/00
    • G11C29/808G11C29/838
    • In order to give all memory blocks the same structure, a redundancy word line and a redundancy bit line are formed in each memory block. A redundancy column selection line is wired in common to the memory blocks. Column redundancy circuits are formed to correspond to respective memory groups each of which consists of a prescribed number of memory blocks, and become effective according to enable signals. A column redundancy selection circuit activates an enable signal according to a block address signal when all row hit signals are deactivated. When one of the row hit signals is activated, the column redundancy selection circuit activates the enable signal corresponding to the activated row hit signal. Since the column redundancy circuit for an arbitrary memory group can be made effective according to the row hit signals, failure relief efficiency can be increased without deteriorating the electric characteristic during an access operation.
    • 为了给予所有存储块相同的结构,在每个存储块中形成冗余字线和冗余位线。 冗余列选择线公共地连接到存储器块。 列冗余电路形成为对应于各自的存储器组,每个存储器组由规定数量的存储块组成,并且根据使能信号变为有效。 当所有行命中信号被去激活时,列冗余选择电路根据块地址信号激活使能信号。 当行命中信号之一被激活时,列冗余选择电路激活对应于激活的行命中信号的使能信号。 由于可以根据行命中信号使任意存储器组的列冗余电路有效,可以在不使访问操作期间的电特性恶化的情况下增加故障排除效率。