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1. 发明申请

US20170358657A1 METHOD FOR MANUFACTURING LATERALLY INSULATED-GATE BIPOLAR TRANSISTOR 有权
公开(公告)号：US20170358657A1
公开(公告)日：2017-12-14
申请号：US15541155
申请日：2015-09-28
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Feng HUANG , Guangtao HAN , Guipeng SUN , Feng LIN , Longjie ZHAO , Huatang LIN , Bing ZHAO , Lixiang LIU , Liangliang PING , Fengying CHEN
IPC分类号： H01L29/66 , H01L29/40 , H01L21/311 , H01L29/739 , H01L29/06 , H01L21/02 , H01L21/265
CPC分类号： H01L29/66325 , H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02318 , H01L21/26513 , H01L21/31116 , H01L29/0653 , H01L29/408 , H01L29/7393 , H01L29/78
摘要： The present invention relates to a method for manufacturing a laterally insulated-gate bipolar transistor, comprising: providing a wafer having an N-type buried layer (10), an STI (40), and a first N well (22)/a first P well (24) which are formed successively from above a substrate; depositing and forming a high-temperature oxide film on the first N well (22) of the wafer; performing thermal drive-in on the wafer and performing photoetching and etching on the high-temperature oxide film to form a mini oxide layer (60); performing photoetching and ion implantation so as to form a second N well (32) inside the first N well (22) and second P wells (34) inside the first N well (22) and the first P well (24); then successively forming a gate oxide layer and a polysilicon gate (72), wherein one end of the gate oxide layer and the polysilicon gate (72) extends onto the second P well (34) inside the first N well (22), and the other end extends onto the mini oxide layer (60) on the second N well (32); and photoetching and injecting N-type ions between the mini oxide layer (60) and the STI (40) adjacent to the mini oxide layer (60) to form a drain electrode, and at the same time forming a source electrode (51) inside the second P well (34).

2. 发明申请

US20170352749A1 LATERAL INSULATED-GATE BIPOLAR TRANSISTOR 有权
公开(公告)号：US20170352749A1
公开(公告)日：2017-12-07
申请号：US15538450
申请日：2015-09-10
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shukun QI
IPC分类号： H01L29/739 , H01L29/08
CPC分类号： H01L29/7394 , H01L29/0834 , H01L29/7393
摘要： A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.

3. 发明授权

US09780084B2 Electrostatic discharge protection structure and fabrication method thereof 有权
公开(公告)号：US09780084B2
公开(公告)日：2017-10-03
申请号：US15055613
申请日：2016-02-28
申请人： CSMC Technologies Fab1 Co., Ltd.
发明人： Yonghai Hu , Meng Dai , Zhongyu Lin , Guangyang Wang
IPC分类号： H01L21/04 , H01L27/02 , H01L29/66 , H01L29/87 , H01L21/762 , H01L21/8232 , H01L21/02 , H01L21/265 , H01L21/3205 , H01L29/40
CPC分类号： H01L27/0255 , H01L21/0223 , H01L21/02255 , H01L21/26513 , H01L21/32055 , H01L21/76202 , H01L21/76224 , H01L21/8232 , H01L27/0248 , H01L29/402 , H01L29/66121 , H01L29/87
摘要： An electrostatic discharge protection structure includes: substrate of a first type of conductivity, well region of a second type of conductivity, substrate contact region in the substrate and of the first type of conductivity, well contact region in the well region and of the second type of conductivity, substrate counter-doped region between the substrate contact region and the well contact region and of the second type of conductivity, well counter-doped region between the substrate contact region and the well contact region and of the first type of conductivity, communication region at a lateral junction between the substrate and the well region, first isolation region between the substrate counter-doped region and the communication region, second isolation region between the well counter-doped region and the communication region, oxide layer having one end on the first isolation region and another end on the substrate, and field plate structure on the oxide layer.

4. 发明授权

US09673193B2 Manufacturing method for reverse conducting insulated gate bipolar transistor 有权
公开(公告)号：US09673193B2
公开(公告)日：2017-06-06
申请号：US14902519
申请日：2014-08-19
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Shuo Zhang , Qiang Rui , Genyi Wang , Xiaoshe Deng
IPC分类号： H01L27/06 , H01L29/66 , H01L29/739 , H01L21/3065 , H01L21/265 , H01L21/304 , H01L29/10 , H01L29/06
CPC分类号： H01L27/0664 , H01L21/263 , H01L21/26513 , H01L21/304 , H01L21/3065 , H01L29/0638 , H01L29/0834 , H01L29/1095 , H01L29/66333 , H01L29/7395
摘要： A manufacturing method for reverse conducting insulated gate bipolar transistor, the manufacturing method is characterized by the use of polysilicon for filling in grooves on the back of a reverse conducting insulated gate bipolar transistor. The parameters of reverse conducting diodes on the back of the reverse conducting insulated gate bipolar transistor can be controlled simply by controlling the doping concentration of the polysilicon accurately, indicating relatively low requirements for process control. The reverse conducting insulated gate bipolar transistor manufacturing method is relatively low in requirements for process control and relatively small in manufacturing difficulty.

5. 发明授权

US09580301B2 MEMS chip and manufacturing method therefor 有权
标题翻译： MEMS芯片及其制造方法
公开(公告)号：US09580301B2
公开(公告)日：2017-02-28
申请号：US14411537
申请日：2013-06-29
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Dan Dai , Xinwei Zhang , Guoping Zhou , Changfeng Xia
IPC分类号： B81B7/00 , B81C1/00
CPC分类号： B81C1/00825 , B81B7/0029 , B81C1/0038 , B81C2201/0167 , B81C2201/053
摘要： A MEMS chip (100) includes a silicon substrate layer (110), a first oxidation layer (120) and a first thin film layer (130). The silicon substrate layer includes a front surface (112) for a MEMS process and a rear surface (114), both the front surface and the rear surface being polished surfaces. The first oxidation layer is mainly made of silicon dioxide and is formed on the rear surface of the silicon substrate layer. The first thin film layer is mainly made of silicon nitride and is formed on the surface of the first oxidation layer. In the above MEMS chip, by sequentially laminating a first oxidation layer and a first thin film layer on the rear surface of a silicon substrate layer, the rear surface is effectively protected to prevent the scratch damage in the course of a MEMS process. A manufacturing method for the MEMS chip is also provided.
摘要翻译： MEMS芯片（100）包括硅衬底层（110），第一氧化层（120）和第一薄膜层（130）。硅衬底层包括用于MEMS工艺的前表面（112）和后表面（114），前表面和后表面都是抛光表面。第一氧化层主要由二氧化硅制成，并形成在硅衬底层的后表面上。第一薄膜层主要由氮化硅制成，并且形成在第一氧化层的表面上。在上述MEMS芯片中，通过在硅衬底层的后表面依次层叠第一氧化层和第一薄膜层，有效地保护后表面以防止在MEMS工艺过程中的划痕损伤。还提供了一种用于MEMS芯片的制造方法。

6. 发明授权

US09431308B2 Critical size compensating method of deep groove etching process 有权
标题翻译：深沟蚀刻工艺的临界尺寸补偿方法
公开(公告)号：US09431308B2
公开(公告)日：2016-08-30
申请号：US14436033
申请日：2013-12-31
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Anna Zhang , Xiaoming Li
IPC分类号： H01L21/66 , H01L21/308 , H01L21/3065
CPC分类号： H01L22/12 , H01L21/3065 , H01L21/308 , H01L21/3083 , H01L22/20
摘要： A critical dimension compensating method of a deep trench etching process includes: obtaining an etching critical dimension difference; compensating an masking layer layout for wafer etching according to a distance between an etching position and the center position of the wafer, and the etching critical dimension difference; and performing a deep trench etching to the wafer according to the compensated masking layer layout. The dimension of the etching patterns of the masking layer layout is compensated by using half of the critical dimension difference as the compensation value, such that the etch rate difference and the etching dimension difference caused by uneven distribution of the critical dimension at different wafer locations during the deep trench etching process are improved, thus greatly improving the uniformity of the critical dimension of the deep trench etching structure.
摘要翻译：深沟槽蚀刻工艺的关键尺寸补偿方法包括：获得蚀刻临界尺寸差; 根据蚀刻位置和晶片的中心位置之间的距离和蚀刻临界尺寸差补偿用于晶片蚀刻的掩模层布局; 以及根据补偿的掩模层布局对晶片执行深沟槽蚀刻。通过使用临界尺寸差的一半作为补偿值来补偿掩模层布局的蚀刻图案的尺寸，使得由不同晶片位置的临界尺寸不均匀分布引起的蚀刻速率差和蚀刻尺寸差异深沟槽蚀刻工艺得到改善，从而大大提高了深沟槽蚀刻结构的临界尺寸的均匀性。

7. 发明授权

US09431241B2 Method for manufacturing a silicon nitride thin film using plasma-enhanced chemical vapor deposition 有权
标题翻译：使用等离子体增强化学气相沉积制造氮化硅薄膜的方法
公开(公告)号：US09431241B2
公开(公告)日：2016-08-30
申请号：US14411999
申请日：2013-07-30
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Zhanxin Li
IPC分类号： H01L21/02 , C23C16/34 , C23C16/505
CPC分类号： H01L21/02274 , C23C16/345 , C23C16/505 , H01L21/0217 , H01L21/02211
摘要： A method for manufacturing a silicon nitride thin film comprises a step of charging silane, ammonia gas and nitrogen gas at an environment temperature below 350° C. to produce and deposit a silicon nitride thin film, wherein a rate of charging silane is 300-350 sccm, a rate of charging ammonia gas is 1000 sccm, a rate of charging nitrogen gas is 1000 sccm; a power of a high frequency source is 0.15˜0.30 KW, a power of a low frequency source is 0.15˜0.30 KW; a reaction pressure is 2.3˜2.6 Torr; a reaction duration is 4˜6 s. The above method for manufacturing a silicon nitride thin film provides a preferable parameter range and preferred parameters for generating a low-stress SIN thin film at low temperatures, achieves manufacture of a low-stress SIN thin film at low temperatures, and thus, better satisfies the situation requiring a low-stress SIN thin film.
摘要翻译：制造氮化硅薄膜的方法包括在低于350℃的环境温度下加入硅烷，氨气和氮气以产生和沉积氮化硅薄膜的步骤，其中填充硅烷的速率为300-350 sccm，氨气的加入速率为1000sccm，氮气的充填速度为1000sccm; 高频源的功率为0.15〜0.30KW，低频源的功率为0.15〜0.30KW; 反应压力为2.3〜2.6乇; 反应时间为4〜6秒。上述制造氮化硅薄膜的方法提供了优选的参数范围和用于在低温下产生低应力SIN薄膜的优选参数，在低温下实现了低应力SIN薄膜的制造，从而更好地满足需要低应力SIN薄膜的情况。

8. 发明授权

US09391133B2 Capacitor and preparation method thereof 有权
标题翻译：电容器及其制备方法
公开(公告)号：US09391133B2
公开(公告)日：2016-07-12
申请号：US14130439
申请日：2012-08-02
申请人： Rengang Qin , Dejin Wang , Boyong He
发明人： Rengang Qin , Dejin Wang , Boyong He
IPC分类号： H01L49/02 , H01L21/02 , C23C16/34
CPC分类号： H01L28/75 , C23C16/345 , H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02271 , H01L28/40
摘要： A capacitor and a method of fabricating thereof are provided. A structure of low pressure tetraethyl orthosilicate—low pressure silicon nitride—low pressure tetraethyl orthosilicate is used in the capacitor to replace the oxide-nitride-oxide structure of the existing capacitor; the capacitor has a relatively high unit capacitance value. Furthermore, the structure of low pressure tetraethyl orthosilicate—low pressure silicon nitride—low pressure tetraethyl orthosilicate is fabricaited by low pressure chemical vapor deposition method at relatively low temperature; thus the heat produced in the whole process is relatively low, which is insufficient to make the semiconductor device shift or make the gate metal layer or the metallized silicon layer peel off. Accordingly, the capacitor and the method of fabricating the capacitor of the present invention can be well applied in the process of the 0.5 μm PIP capacitor or below 0.5 μm.
摘要翻译：提供电容器及其制造方法。在电容器中使用低压四乙基原硅酸盐低压氮化硅 - 低压四乙基原硅酸盐的结构来代替现有电容器的氧化物 - 氮化物 - 氧化物结构; 电容器具有相对高的单位电容值。此外，低压四乙基原硅酸盐低压氮化硅 - 低压四乙基原硅酸盐的结构是通过低温化学气相沉积法在较低的温度下制得的; 因此在整个过程中产生的热量相对较低，这不足以使半导体器件移位或使栅极金属层或金属化硅层剥离。因此，本发明的电容器和制造电容器的方法可以很好地应用于0.5μmPIP电容器或0.5μm以下的工艺。

9. 发明申请

US20150332981A1 METHOD FOR WAFER ETCHING IN DEEP SILICON TRENCH ETCHING PROCESS 有权
标题翻译：深层硅凝胶蚀刻过程中的蚀刻方法
公开(公告)号：US20150332981A1
公开(公告)日：2015-11-19
申请号：US14435955
申请日：2013-12-31
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Anna ZHANG , Xiaoming LI
IPC分类号： H01L21/66 , H01L21/683 , H01L21/3065
CPC分类号： H01L22/26 , H01L21/3065 , H01L21/6831
摘要： A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S110); b. performing the sub-steps of a main process for the wafer, and the time for the sub-steps of the main process being shorter than the time required by the wafer main process; c. releasing the electrostatic adsorption of the electrostatic chuck on the wafer; d. determining whether the cumulative time of the sub-steps of the main process reaches a predetermined threshold or not, if so, performing the step e (S150), and if not, repeating the operations in the steps a to c (S140); and e. ending a wafer manufacturing process. The etching method avoids the wafer from continuous contact with the electrostatic chuck, reduces electrostatic accumulation on the surface of the wafer, and therefore solves the problem of resist reticulation on the surface of the wafer in the DSIE process.
摘要翻译：在深硅沟槽蚀刻工艺中的晶片蚀刻方法包括以下步骤：a。使用静电卡盘静电吸收晶片，并稳定工艺所需的气氛（S110）; b。执行晶片主工艺的子步骤，并且主工艺的子步骤的时间比晶片主工艺所需的时间短; C。释放静电吸盘在晶片上的静电吸附; d。确定主处理的子步骤的累积时间是否达到预定阈值（如果是），执行步骤e（S150），如果不是则重复步骤a至c中的操作（S140）; 和e。结束晶圆制造工艺。蚀刻方法避免了晶片与静电卡盘的连续接触，减少了晶片表面上的静电积累，因此解决了DSIE工艺中晶片表面的抗网纹问题。

10. 发明申请

US20150227048A1 PHOTOLITHOGRAPHY METHOD AND SYSTEM BASED ON HIGH STEP SLOPE 有权
标题翻译：基于高阶梯度的光刻方法和系统
公开(公告)号：US20150227048A1
公开(公告)日：2015-08-13
申请号：US14435945
申请日：2013-09-03
申请人： CSMC TECHNOLOGIES FAB1 CO., LTD.
发明人： Jiale Su
IPC分类号： G03F7/20
CPC分类号： G03F7/2035 , G03F1/38 , G03F7/203
摘要： A photolithography method and system based on a high step slope are provided. The method includes: S1, manufacturing a sacrificial layer with a high step slope on a substrate; S2, adopting a spin-on PR coating process to cover the sacrificial layer with a photoresist layer to form a photolithographic layer; S3, forming a mask pattern and a compensation pattern on a mask; and S4, performing photolithography processes, by a photolithography machine, on the photolithographic layer. By forming a slope-top compensation pattern and a slope compensation pattern on a mask to perform photolithography on the substrate of a sacrificial layer, a relatively wide compensation pattern is set in a part of the top of the slope with a small thickness, thereby compensating the overexposure at the top of the slope, reducing the error in the photolithographic pattern, and improving the precision of photolithography of the high step slope.
摘要翻译：提供了一种基于高阶斜率的光刻方法和系统。该方法包括：S1，在衬底上制造具有高阶跃斜率的牺牲层; S2，采用旋涂PR涂覆工艺以用光致抗蚀剂层覆盖牺牲层以形成光刻层; S3，在掩模上形成掩模图案和补偿图案; 和S4，通过光刻机在光刻层上进行光刻工艺。通过在掩模上形成斜坡补偿图案和斜率补偿图案以在牺牲层的基板上进行光刻，在斜面的顶部的一部分中以较小的厚度设置相对较宽的补偿图案，从而补偿斜坡顶部过度曝光，降低了光刻图案的误差，提高了高阶斜坡光刻的精度。

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