专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明授权

US07642204B2 Methods of forming fluorine doped insulating materials 失效
标题翻译：形成氟掺杂绝缘材料的方法
公开(公告)号：US07642204B2
公开(公告)日：2010-01-05
申请号：US10769430
申请日：2004-01-30
申请人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
发明人： Anand Srinivasan , Gurtej Sandhu , Ravi Iyer
IPC分类号： H01L21/316
CPC分类号： H01L21/02131 , C23C16/401 , H01L21/02271 , H01L21/31629
摘要： In one aspect, the invention includes a method of forming an insulating material comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising a Si, F and ozone within the reaction chamber; and c) depositing an insulating material comprising fluorine, silicon and oxygen onto the substrate from the reactants. In another aspect, the invention includes a method of forming a boron-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising Triethoxy fluorosilane, a boron-containing precursor, and ozone within the reaction chamber; and c) depositing a boron-doped silicon oxide having Si—F bonds onto the substrate from the reactants. In yet another aspect, the invention includes a method of forming a phosphorus-doped silicon oxide having Si—F bonds, comprising: a) providing a substrate within a reaction chamber; b) providing reactants comprising triethoxy fluorosilane, a phosphorus-containing precursor, and ozone within the reaction chamber; and c) depositing a phosphorus-doped silicon oxide having Si—F bonds onto the substrate from the reactants.
摘要翻译：一方面，本发明包括一种形成绝缘材料的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含Si，F和臭氧的反应物; 以及c）从所述反应物沉积包含氟，硅和氧的绝缘材料到所述衬底上。另一方面，本发明包括形成具有Si-F键的掺硼氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含硼前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的掺硼氧化硅到所述衬底上。另一方面，本发明包括形成具有Si-F键的磷掺杂氧化硅的方法，包括：a）在反应室内提供衬底; b）在反应室内提供包含三乙氧基氟硅烷，含磷前体和臭氧的反应物; 以及c）从所述反应物沉积具有Si-F键的磷掺杂的氧化硅到所述衬底上。

72. 发明申请

US20090294878A1 CIRCUITRY AND GATE STACKS 审中-公开
标题翻译：电路和门架
公开(公告)号：US20090294878A1
公开(公告)日：2009-12-03
申请号：US12537577
申请日：2009-08-07
申请人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
发明人： Zhiping Yin , Ravi Iyer , Thomas R. Glass , Richard Holscher , Ardavan Niroomand , Linda K. Somerville , Gurtej S. Sandhu
IPC分类号： H01L29/78
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/28123 , H01L21/32139
摘要： The present invention includes semiconductor circuitry. Such circuitry encompasses a metal silicide layer over a substrate and a layer comprising silicon, nitrogen and oxygen in physical contact with the metal silicide layer. The present invention also includes a gate stack which encompasses a polysilicon layer over a substrate, a metal silicide layer over the polysilicon layer, an antireflective material layer over the metal silicide layer, a silicon nitride layer over the antireflective material layer, and a layer of photoresist over the silicon nitride layer, for photolithographically patterning the layer of photoresist to form a patterned masking layer from the layer of photoresist and transferring a pattern from the patterned masking layer to the silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer. The patterned silicon nitride layer, antireflective material layer, metal silicide layer and polysilicon layer encompass a gate stack.
摘要翻译：本发明包括半导体电路。这种电路包括衬底上的金属硅化物层和与金属硅化物层物理接触的包含硅，氮和氧的层。本发明还包括一个栅极堆叠，其包围衬底上的多晶硅层，多晶硅层上的金属硅化物层，金属硅化物层上的抗反射材料层，抗反射材料层上的氮化硅层，以及一层在氮化硅层上的光致抗蚀剂，用于光刻地图案化该光致抗蚀剂层以从光致抗蚀剂层形成图案化掩模层，并将图案从图案化掩模层转移到氮化硅层，抗反射材料层，金属硅化物层和多晶硅层。图案化氮化硅层，抗反射材料层，金属硅化物层和多晶硅层包围栅极堆叠。

73. 发明授权

US07262503B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US07262503B2
公开(公告)日：2007-08-28
申请号：US11026822
申请日：2004-12-29
申请人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
发明人： Werner Juengling , Kirk D. Prall , Ravi Iyer , Gurtej S. Sandhu , Guy Blalock
IPC分类号： H01L23/48
CPC分类号： H01L23/5222 , H01L21/02115 , H01L21/02118 , H01L21/02203 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/02362 , H01L21/31695 , H01L21/7682 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/76834 , H01L23/5329 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. In another aspect, the invention includes an insulating material adjacent a conductive electrical component, the insulating material comprising a matrix and at least one void within the matrix. In another aspect, the invention includes an insulating region between a pair of conductive electrical components comprising: a) a support member between the conductive electrical components, the support member not comprising a conductive interconnect; and b) at least one void between the support member and each of the pair of conductive electrical components.
摘要翻译：本发明包括在导电元件之间形成绝缘材料的方法。在一个方面，本发明包括形成邻近导电电气部件的材料的方法，该方法包括：a）部分蒸发物质以形成邻近导电电气部件的基体，所述基质在其内具有至少一个空隙。另一方面，本发明包括一种在一对导电电气部件之间形成材料的方法，包括以下步骤：a）在质量体内形成一对导电的电气部件，并由质量块的一部分分隔; b）在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及c）将所述物质的所述膨胀物蒸发至有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙的程度。在另一方面，本发明包括与导电电气部件相邻的绝缘材料，所述绝缘材料包含基体和所述基体内的至少一个空隙。在另一方面，本发明包括在一对导电电气部件之间的绝缘区域，包括：a）导电电气部件之间的支撑部件，所述支撑部件不包括导电互连; 以及b）所述支撑构件和所述一对导电电气部件中的每一个之间的至少一个空隙。

74. 发明申请

US20070105357A1 SILICIDED RECESSED SILICON 有权
标题翻译：硅化硅
公开(公告)号：US20070105357A1
公开(公告)日：2007-05-10
申请号：US11614802
申请日：2006-12-21
申请人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
IPC分类号： H01L21/3205 , H01L23/48
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

75. 发明授权

US07214621B2 Methods of forming devices associated with semiconductor constructions 有权
标题翻译：形成与半导体结构相关的器件的方法
公开(公告)号：US07214621B2
公开(公告)日：2007-05-08
申请号：US11131994
申请日：2005-05-18
申请人： Hasan Nejad , Gordon A. Haller , Thomas Arthur Figura , Ravi Iyer
发明人： Hasan Nejad , Gordon A. Haller , Thomas Arthur Figura , Ravi Iyer
IPC分类号： H01L21/8244
CPC分类号： H01L27/10894 , H01L27/10876 , H01L27/10897 , Y10S439/917
摘要： The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.
摘要翻译：本发明包括形成与半导体结构相关的器件的方法。在示例性方法中，利用通常的处理步骤来形成完全硅化的凹陷阵列存取栅极和部分硅化的外围晶体管栅极。

76. 发明授权

US07109115B2 Methods of providing ohmic contact 有权
标题翻译：提供欧姆接触的方法
公开(公告)号：US07109115B2
公开(公告)日：2006-09-19
申请号：US11071922
申请日：2005-03-04
申请人： Ravi Iyer , Yongjun Jeff Hu , Luan Tran , Brent Gilgen
发明人： Ravi Iyer , Yongjun Jeff Hu , Luan Tran , Brent Gilgen
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/76849 , H01L21/76855 , H01L21/7687 , H01L21/76889 , H01L23/485 , H01L27/10855 , H01L28/84 , H01L28/90 , H01L29/456 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.
摘要翻译：使用覆盖含硅材料的第一耐火金属材料和覆盖第一难熔金属材料的第二难熔金属材料来降低与含硅材料的接触电阻。每种难熔金属材料是含有难熔金属和杂质的导电材料。第一难熔金属材料是富含金属的材料，其含量低于化学计量水平的杂质。与第一难熔金属材料相比，第二难熔金属材料对杂质的亲和力较低。因此，第二难熔金属材料可以在退火或其它暴露于热的过程中用作杂质供体。这种杂质向第一难熔金属材料的净迁移限制了第一难熔金属材料和下面的含硅材料之间的金属硅化物界面的生长，从而提供与耐热性的欧姆接触。

77. 发明申请

US20060104303A1 Packet coalescing 有权
公开(公告)号：US20060104303A1
公开(公告)日：2006-05-18
申请号：US10991239
申请日：2004-11-16
申请人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04L12/28
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

78. 发明授权

US07041548B1 Methods of forming a gate stack that is void of silicon clusters within a metallic silicide film thereof 失效
标题翻译：在其金属硅化物膜内形成无硅团簇的栅叠层的方法
公开(公告)号：US07041548B1
公开(公告)日：2006-05-09
申请号：US09614113
申请日：2000-07-12
申请人： Pai-Hung Pan , Louie Liu , Ravi Iyer
发明人： Pai-Hung Pan , Louie Liu , Ravi Iyer
IPC分类号： H01L21/8238
CPC分类号： H01L21/28052
摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.
摘要翻译：一种用于形成栅堆叠的方法，其通过在形成期间的温度降低来最小化或消除在栅叠层形成期间对栅介质层和/或硅衬底的损坏。温度降低防止在栅极堆叠中的金属硅化物膜内形成硅团簇，这已被发现在栅极蚀刻步骤期间造成损坏。本发明还包括在栅极蚀刻步骤之前分散硅簇的方法。

79. 发明授权

US07038318B2 Compound structure for reduced contact resistance 失效
公开(公告)号：US07038318B2
公开(公告)日：2006-05-02
申请号：US10689894
申请日：2003-10-21
申请人： Ravi Iyer , Yongjun Jeff Hu , Luan Tran , Brent Gilgen
发明人： Ravi Iyer , Yongjun Jeff Hu , Luan Tran , Brent Gilgen
IPC分类号： H01L29/40
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/76849 , H01L21/76855 , H01L21/7687 , H01L21/76889 , H01L23/485 , H01L27/10855 , H01L28/84 , H01L28/90 , H01L29/456 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： Various embodiments of the invention described herein reduce contact resistance to a silicon-containing material using a first refractory metal material overlying the silicon-containing material and a second refractory metal material overlying the first refractory metal material. Each refractory metal material is a conductive material containing a refractory metal and an impurity. The first refractory metal material is a metal-rich material, containing a level of its impurity at less than a stoichiometric level. The second refractory metal material has a lower affinity for the impurities than does the first refractory metal material. The second refractory metal material can thus serve as an impurity donor during an anneal or other exposure to heat. This net migration of the impurities to the first refractory metal material limits growth of a metal silicide interface between the first refractory metal material and the underlying silicon-containing material, thereby providing ohmic contact with attendant thermal tolerance.

80. 发明申请

US20060029736A1 Method to reduce fixed charge in CVD ozone deposited films 失效
标题翻译：降低CVD臭氧沉积膜中固定电荷的方法
公开(公告)号：US20060029736A1
公开(公告)日：2006-02-09
申请号：US11192326
申请日：2005-07-27
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： C23C16/00
CPC分类号： C23C16/401
摘要： Disclosed is a CVD ozone (O3) deposition process, with the preferred embodiment comprising the steps of disposing a substrate in a chemical vapor deposition chamber and exposing the substrate surface to a SiO2 precursor gas, a carrier gas, and optionally a dopant gas in the presence of ozone and exposing the reaction volume of the gases above the substrate surface to a high intensity light source, to increase the functional atomic oxygen concentration and reduce the fixed charge in the deposited films.
摘要翻译：公开了一种CVD臭氧（O 3 N 3）沉积工艺，优选的实施方案包括以下步骤：将基材设置在化学气相沉积室中，并将基材表面暴露于SiO 2 SUB>前体气体，载气和任选的掺杂剂气体，并将基板表面上方的气体的反应体积暴露于高强度光源，以增加功能原子氧浓度并降低固定电荷在沉积膜中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式