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71. 发明授权

US09041576B2 Circuit and method 有权
标题翻译：电路和方法
公开(公告)号：US09041576B2
公开(公告)日：2015-05-26
申请号：US13976649
申请日：2012-12-20
申请人： Intel Mobile Communications GmbH
发明人： Bernd-Ulrich Klepser , Markus Scholz , Zdravko Boos , Thomas Mayer
IPC分类号： H03M1/66 , H03M1/74 , H04L27/20 , H04L27/36 , H03M1/82
CPC分类号： H03M1/74 , H03M1/82 , H04L27/2003 , H04L27/361
摘要： Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.
摘要翻译：本发明的实施例产生具有数字 - 时间转换器的电路，其具有用于接收高频信号的高频输入端，用于接收第一数字信号的数字输入端和用于提供高频信号的高频输出端时间延迟版本的HF信号。此外，电路具有用于提供高频信号的振荡器装置，具有用于调节高频信号的频率的锁相环。数字 - 时间转换器被设计为基于在其数字输入处接收的第一数字信号按时间顺序延迟所接收的高频信号。

72. 发明授权

US08970418B1 High output power digital-to-analog converter system 有权
标题翻译：高输出功率数模转换器系统
公开(公告)号：US08970418B1
公开(公告)日：2015-03-03
申请号：US14222223
申请日：2014-03-21
申请人： Analog Devices, Inc.
发明人： Bernd Schafferer , Bing Zhao
IPC分类号： H03M1/66 , H03M1/74
CPC分类号： H03M1/74 , H03M1/747
摘要： The present disclosure discloses a digital-to-analog converter (DAC) design which is suitable for providing a high output power high-speed DAC, e.g., in radio frequency applications. The DAC design utilizes a parallel DAC structure, e.g., having 8 parallel DACs and an aggregate current output, to provide a high and programmable current output (in some implementations, up to 512 mA or more). The parallel DAC structure alleviates the design problems which exist in trying to output a high amount of current using a single DAC. The DAC design further utilizes a hybrid structure which integrates the signal chain for a more reliable system. In some embodiments, the hybrid structure uses a CMOS process for the current sources and switches and a GaAs cascode stage for combining the outputs to optimally leverage the advantages of both technologies. The result is a highly efficient DAC (with peak output power programmable up to 29 dBm or more).
摘要翻译：本公开公开了一种数字 - 模拟转换器（DAC）设计，其适用于例如在射频应用中提供高输出功率高速DAC。 DAC设计利用并行DAC结构，例如具有8个并行DAC和聚合电流输出，以提供高且可编程的电流输出（在一些实现中，高达512mA或更多）。并行DAC结构减轻了使用单个DAC输出大量电流时存在的设计问题。 DAC设计进一步利用混合结构，将信号链集成在一个更可靠的系统中。在一些实施例中，混合结构使用用于电流源和开关的CMOS工艺和用于组合输出的GaAs级联级，以最佳地利用两种技术的优点。结果是高效率的DAC（峰值输出功率可编程高达29 dBm或更高）。

73. 发明申请

US20150048959A1 LOCALIZED DYNAMIC ELEMENT MATCHING AND DYNAMIC NOISE SCALING IN DIGITAL-TO-ANALOG CONVERTERS (DACS) 有权
标题翻译：数字模拟转换器（DACS）中的本地化动态元件匹配和动态噪声调节
公开(公告)号：US20150048959A1
公开(公告)日：2015-02-19
申请号：US14458439
申请日：2014-08-13
申请人： MaxLinear, Inc.
发明人： Jianyu Zhu
IPC分类号： H03M1/06 , H03M1/74
CPC分类号： H03M1/08 , H03M1/0617 , H03M1/066 , H03M1/66 , H03M1/74
摘要： Methods and systems are provided for using localized dynamic element matching (DEM) and/or dynamic noise scaling (DNS) in digital-to-analog converters (DACs). Adaptive (localized) DEM may be applied in a DAC, by selecting one or more of a plurality DAC elements in the DAC, forcing the selected one or more of the plurality of DAC elements not to switch during digital-to-analog conversions, and scrambling remaining one or more of plurality of DAC elements when generating an output of the DAC. The adaptive DEM may be applied when the DAC input is backed off from full-scale. DNS may be applied in a DAC, by adaptively selecting one or more of a plurality DAC elements in the DAC and switching off the selected one or more of the plurality DAC elements such that the selected one or more of the plurality DAC elements do not contribute to generating an output of the DAC.
摘要翻译：提供了在数模转换器（DAC）中使用局部动态元素匹配（DEM）和/或动态噪声缩放（DNS）的方法和系统。可以通过选择DAC中的多个DAC元件中的一个或多个DAC来迫使所选择的一个或多个DAC元件在数模转换期间不切换，自适应（局部）DEM可以应用于DAC中;以及当产生DAC的输出时，扰乱剩余一个或多个DAC元件。当DAC输入从满量程退出时，可以应用自适应DEM。 DNS可以通过自适应地选择DAC中的多个DAC元件中的一个或多个并且关闭所选择的多个DAC元件中的一个或多个，使得所选择的一个或多个DAC元件不贡献以产生DAC的输出。

74. 发明授权

US08928512B2 Digital to analog converter and method for controlling current source array in digital to analog converter 有权
标题翻译：数模转换器和数模转换器电流源阵列控制方法
公开(公告)号：US08928512B2
公开(公告)日：2015-01-06
申请号：US14142597
申请日：2013-12-27
申请人： Huawei Technologies Co., Ltd.
发明人： Haiquan Yuan , Peng Gao
IPC分类号： H03M1/66 , H03M1/68 , H03M1/74
CPC分类号： H03M1/685 , H03M1/747
摘要： A digital to analog converter and a method for controlling a current source array in a digital to analog converter relate to the field of electronics technologies, and are used to reduce a system error. The digital to analog converter includes: a decoding module, a switch array, and a current source array, where the decoding module is configured to generate a 2n−1-bit first temperature code by using high n bits of an input 2n-bit binary digital signal, generate a 2n−1-bit second temperature code by using low n bits of the 2n-bit binary digital signal, and control, by using the 2n−1-bit first temperature code and the 2n−1-bit second temperature code, a working sequence of 2n×2n−1 unit switches.
摘要翻译：数模转换器和用于控制数模转换器中的电流源阵列的方法涉及电子技术领域，并且用于减少系统错误。数模转换器包括：解码模块，开关阵列和电流源阵列，其中解码模块被配置为通过使用输入的2n位二进制数的高n位来产生2n-1位第一温度码数字信号，通过使用2n位二进制数字信号的低n位产生2n-1位第二温度码，并且通过使用2n-1位第一温度码和2n-1位第二温度代码，2n×2n-1单位开关的工作顺序。

75. 发明授权

US08912938B1 Converter and method of controlling the same 有权
标题翻译：转换器和控制方法
公开(公告)号：US08912938B1
公开(公告)日：2014-12-16
申请号：US14166829
申请日：2014-01-28
申请人： Delta Electronics (Shanghai) Co., Ltd.
发明人： Hao Lu , Kuang Sheng
IPC分类号： H03M1/66 , H03M1/06 , H02M3/156 , H03M1/74 , H02M3/158 , H02M3/157
CPC分类号： H02M3/157 , H02M3/156 , H02M3/1588 , H03M1/747
摘要： A converter and a method for controlling a converter are disclosed herein, in which the converter includes a converting circuit, a current sensing circuit, a digital-to-analog converting circuit, a slope compensation circuit and a comparator circuit. The slope compensation circuit is independent from the digital-to-analog converting circuit, and the slope compensation circuit exclusively generates an analog slope compensation signal. The comparator circuit compares an analog signal generated by the digital-to-analog converting circuit with the superimposition of the analog slope compensation signal and a current sensing signal generated by the current sensing circuit or compares the current sensing signal with the superimposition of the analog slope compensation signal and the analog signal to generate a comparator output signal for a control operation of the converting circuit.
摘要翻译：本文公开了A转换器和用于控制转换器的方法，其中转换器包括转换电路，电流感测电路，数模转换电路，斜率补偿电路和比较器电路。斜率补偿电路独立于数模转换电路，斜坡补偿电路专门生成模拟斜率补偿信号。比较器电路将由数模转换电路产生的模拟信号与模拟斜率补偿信号的叠加与由电流感测电路产生的电流感测信号进行比较，或将电流感测信号与模拟斜率的叠加补偿信号和模拟信号，以产生用于转换电路的控制操作的比较器输出信号。

76. 发明授权

US08907831B1 High-resolution digital to analog converter 有权
标题翻译：高分辨率数模转换器
公开(公告)号：US08907831B1
公开(公告)日：2014-12-09
申请号：US14136728
申请日：2013-12-20
申请人： Maxim Integrated Products, Inc.
发明人： Syed Amir Aftab
IPC分类号： H03M1/66 , H03M1/68 , H03M1/00 , H03M1/78 , H03M1/74
CPC分类号： H03M1/68 , H03M1/00 , H03M1/687 , H03M1/747 , H03M1/765 , H03M1/785
摘要： A system includes an N-bit digital-to-analog converter and an M-bit sub-digital-to-analog converter. The N-bit digital-to-analog converter includes 2N resistances connected in series across first and second reference voltages and converts N most significant bits of B bits of data. The M-bit sub-digital-to-analog converter converts M least significant bits of the B bits of data. The M-bit sub-digital-to-analog converter includes a first converter that converts a voltage across one of the 2N resistances to a first current, a current-mode digital-to-analog converter that interpolates the first current and outputs a second current, and a second converter that converts the second current to an output voltage representing the N most significant bits and the M least significant bits of the B bits of data.
摘要翻译：一个系统包括一个N位数模转换器和一个M位子数模转换器。 N位数模转换器包括在第一和第二参考电压上串联连接的2N个电阻，并且转换B位数据的N个最高有效位。 M位子数字到模拟转换器转换B位数据的M个最低有效位。 M位子数模转换器包括将2N个电阻中的一个电压转换为第一电流的第一转换器，内插第一电流的电流模式数模转换器，并输出第二电流电流和第二转换器，其将第二电流转换成表示数据的B位的N个最高有效位和M个最低有效位的输出电压。

77. 发明授权

US08896471B1 Conversion of a discrete-time quantized signal into a continuous-time, continuously variable signal 有权
标题翻译：将离散时间量化信号转换为连续时间连续可变信号
公开(公告)号：US08896471B1
公开(公告)日：2014-11-25
申请号：US13647301
申请日：2012-10-08
申请人： Syntropy Systems, LLC
发明人： Christopher Pagnanelli
IPC分类号： H03M3/00 , H03M1/74
CPC分类号： H03M3/30 , H03M1/747 , H03M3/358 , H03M3/50 , H03M3/502 , H03M7/3026 , H03M7/3033
摘要： Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.
摘要翻译：尤其提供了用于将离散时间量化信号转换成连续时间连续可变信号的系统，装置，方法和技术。示例性转换器优选地包括：（1）多个过采样转换器，每个处理不同的频带，并行操作; （2）多速率（即多相）Δ-Σ调制器（优选二阶或更高）; （3）多位量化器; （4）多位到可变电平信号转换器，如电阻梯形网络或电流源网络; （5）自适应非线性比特映射以补偿多比特到可变电平信号转换器中的不匹配（例如，通过模拟这样的失配，然后将所得到的噪声移动到频率范围，其中将被滤波掉相应的带通（重建）滤波器）; （6）多频带（例如可编程噪声传递函数响应）带通Δ-Σ调制器; 和/或（7）用于消除由模拟信号带通（重构）滤波器组引入的噪声和失真的数字预失真线性化器（DPL）。

78. 发明授权

US08872685B2 Techniques to reduce harmonic distortions of impedance attenuators for low-power wideband high-resolution DACs 有权
标题翻译：降低低功耗宽带高分辨率DAC阻抗衰减器谐波失真的技术
公开(公告)号：US08872685B2
公开(公告)日：2014-10-28
申请号：US13839763
申请日：2013-03-15
申请人： QUALCOMM Incorporated
发明人： Tongyu Song , Sang Min Lee , Derui Kong , Dongwon Seo
IPC分类号： H03M1/00 , H03M1/74
CPC分类号： H03M1/74 , H03F3/19 , H03F3/211 , H03F3/245 , H03F3/45192 , H03F3/4565 , H03F3/72 , H03F2203/45466 , H03F2203/45512 , H03F2203/45562 , H03F2203/45631 , H03F2203/45634 , H03F2203/45644 , H03F2203/45686 , H03F2203/45701 , H03F2203/45702 , H03F2203/7236 , H03M1/0614
摘要： A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.
摘要翻译：数模转换器（DAC）部分地包括响应于数字信号向一对当前求和节点提供电流的多个输入级，以及耦合在当前求和节点和输出端之间的阻抗衰减器的DAC。除了其他功能之外，阻抗衰减器还适用于增加输出负载的阻抗范围，以解决由于工艺，电压和温度的变化而导致的输出负载阻抗的变化，并且将由总和看到的阻抗解耦节点从负载阻抗。阻抗衰减器还包括具有可编程共模增益带宽的差分输入差分输出放大器，以控制放大器的谐波失真。阻抗衰减器可选地包括一对交叉耦合电容器，以控制放大器的谐波失真。

79. 发明申请

US20140002287A1 Circuit and Method 有权
标题翻译：电路和方法
公开(公告)号：US20140002287A1
公开(公告)日：2014-01-02
申请号：US13976649
申请日：2012-12-20
申请人： Bernd-Ulrich Klepser , Markus Scholz , Zdravko Boos , Thomas Mayer
发明人： Bernd-Ulrich Klepser , Markus Scholz , Zdravko Boos , Thomas Mayer
IPC分类号： H03M1/74
CPC分类号： H03M1/74 , H03M1/82 , H04L27/2003 , H04L27/361
摘要： Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input.
摘要翻译：本发明的实施例产生具有数字 - 时间转换器的电路，其具有用于接收高频信号的高频输入端，用于接收第一数字信号的数字输入端和用于提供高频信号的高频输出端时间延迟版本的HF信号。此外，电路具有用于提供高频信号的振荡器装置，具有用于调节高频信号的频率的锁相环。数字 - 时间转换器被设计为基于在其数字输入处接收的第一数字信号按时间顺序延迟所接收的高频信号。

80. 发明申请

US20080252505A1 Read and Write Interface Communications Protocol for Digital-to-Analog Signal Converter with Non-Volatile Memory 有权
标题翻译：具有非易失性存储器的数模转换信号转换器的读写接口通信协议
公开(公告)号：US20080252505A1
公开(公告)日：2008-10-16
申请号：US12017582
申请日：2008-01-22
申请人： Thomas Youbok Lee , Jonathan Jackson , John Austin , Andrew Swaneck , Yann Johner
发明人： Thomas Youbok Lee , Jonathan Jackson , John Austin , Andrew Swaneck , Yann Johner
IPC分类号： H03M1/74
CPC分类号： H03M1/66
摘要： A mixed signal device, e.g., digital-to-analog converter (DAC) device has a serial interface communication protocol that accesses volatile and/or nonvolatile memory and allows a preprogrammed output voltage whenever the mixed signal device is powered-up. However, unlike conventional DAC devices, DAC devices with non-volatile memory may need special interface communication protocols for effective operation of the DAC device and communications between a system master controller unit (MCU). Interface communications protocols that do not violate standard serial bus communications protocols are provided for communicating between the volatile and non-volatile memories of the DAC device so that the MCU may access the DAC device's memories (non-volatile and/or volatile memories).
摘要翻译：混合信号装置，例如数模转换器（DAC）装置具有串行接口通信协议，该协议访问易失性和/或非易失性存储器，并且每当混合信号装置通电时允许预编程的输出电压。然而，与传统DAC器件不同，具有非易失性存储器的DAC器件可能需要特殊的接口通信协议来有效地操作DAC器件以及系统主控制器单元（MCU）之间的通信。提供了不违反标准串行总线通信协议的接口通信协议，用于在DAC设备的易失性和非易失性存储器之间进行通信，以便MCU可以访问DAC设备的存储器（非易失性和/或易失性存储器）。

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