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61. 发明申请

US20080300299A1 Application of Eriocalyxin B in the Manufacture of Medicaments For Treating Leukemia 审中-公开
标题翻译：胭脂红素B在制造治疗白血病药物中的应用
公开(公告)号：US20080300299A1
公开(公告)日：2008-12-04
申请号：US12092914
申请日：2006-10-08
申请人： Sai-juan Chen , Zhu Chen , Lan Wang , Wei-li Zhao , Han-dong Sun
发明人： Sai-juan Chen , Zhu Chen , Lan Wang , Wei-li Zhao , Han-dong Sun
IPC分类号： A61K31/352 , A61P35/02
CPC分类号： A61K31/352
摘要： The use of eriocalyxin B in the manufacture of medicaments for treating leukemia, wherein the leukemia include leukemia containing AML1-ETO fusion protein, acute promyelocytic leukemia, acute myelocytic leukemia and lymphocytic leukemia. Eriocalyxin B increases the level of peroxidate and influences the phosphorylation and degradation of IκBα to prevent NF-κB from getting into the nucleus in order to inhibition NF-κB pathway. Eriocalyxin B can decrease the phosphorylation of ERI1/2 and inhibit MAPK pathway. Eriocalyxin B can extend the life span of mice and decrease tumor volume in mice model of C57 leukemia and tumor transplantation.
摘要翻译：在制备用于治疗白血病的药物中使用调色素B，其中白血病包括含有AML1-ETO融合蛋白的白血病，急性早幼粒细胞白血病，急性骨髓性白血病和淋巴细胞性白血病。 Eriocalyxin B增加过氧化物的水平，并影响IkappaBalpha的磷酸化和降解，以防止NF-κB进入细胞核以抑制NF-κB通路。 Eriocalyxin B可以减少ERI1 / 2的磷酸化并抑制MAPK通路。 Eriocalyxin B可以延长小鼠的寿命，并减少C57白血病和肿瘤移植的小鼠模型中的肿瘤体积。

62. 发明申请

US20080146489A1 Regional delivery of therapeutic agents for the treatment of vascular diseases 审中-公开
标题翻译：用于治疗血管疾病的治疗剂的区域递送
公开(公告)号：US20080146489A1
公开(公告)日：2008-06-19
申请号：US11639512
申请日：2006-12-15
申请人： Stephen D. Pacetti , Paul M. Consigny , Ronald W. Heil , Florian Niklas Ludwig , Dariush Davalian , Li Zhao , Irina Astafieva , Jinping Wan , Fozan El-Nounou , Katsuyuki Murase , Syed F.A. Hossainy , Rachel Bright , Jeffrey Ellis
发明人： Stephen D. Pacetti , Paul M. Consigny , Ronald W. Heil , Florian Niklas Ludwig , Dariush Davalian , Li Zhao , Irina Astafieva , Jinping Wan , Fozan El-Nounou , Katsuyuki Murase , Syed F.A. Hossainy , Rachel Bright , Jeffrey Ellis
IPC分类号： A61F2/06 , A61K31/27 , A61K31/44 , A61K31/56 , A61K31/66 , A61K38/02 , A61P9/00
CPC分类号： A61M25/1002 , A61F2/82 , A61F2250/0067 , A61K31/27 , A61K31/44 , A61K31/56 , A61K31/66 , A61K38/1709 , A61L29/08 , A61L29/16 , A61L31/08 , A61L31/16 , A61L2300/112 , A61L2300/216 , A61L2300/252 , A61L2300/40 , A61L2300/41 , A61L2300/416 , A61L2300/606 , A61L2300/62 , A61M25/10 , A61M37/0015 , A61M2025/105 , A61M2025/1086 , A61M2037/0023 , A61M2037/0061 , A61M2210/12
摘要： The present invention relates to the regional delivery of therapeutic agents for the treatment of vascular diseases wherein regional delivery refers to delivery of a therapeutically effective amount of the therapeutic agent to an area of the vessel that includes not only afflicted tissue but non-afflicted tissue at the periphery of the afflicted tissue as well.
摘要翻译：本发明涉及用于治疗血管疾病的治疗剂的区域递送，其中区域递送是指将治疗有效量的治疗剂递送至血管的区域，该区域不仅包括受到损伤的组织而且包括非折磨组织受影响组织的外围也是如此。

63. 发明申请

US20080040555A1 Selectively inclusive cache architecture 有权
标题翻译：选择性包容性缓存架构
公开(公告)号：US20080040555A1
公开(公告)日：2008-02-14
申请号：US11503777
申请日：2006-08-14
申请人： Ravishankar Iyer , Li Zhao , Srihari Makineni , Donald Newell
发明人： Ravishankar Iyer , Li Zhao , Srihari Makineni , Donald Newell
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831
摘要： In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level cache may be maintained inclusively with a directory portion of the second level cache. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在与第一级高速缓存耦合的第二级高速缓存中的数据非包含地维护第一级高速缓存中的数据的方法。同时，可以与第二级高速缓存的目录部分一起保持与第一级高速缓存中的数据相关联的目录信息的至少一部分。描述和要求保护其他实施例。

64. 发明授权

US6032895A Collared hub pin for a tape cartridge 失效
标题翻译：磁带盒的卡圈式针脚
公开(公告)号：US6032895A
公开(公告)日：2000-03-07
申请号：US219254
申请日：1998-12-22
申请人： David A. Krula , Tom Kao , Li Zhao
发明人： David A. Krula , Tom Kao , Li Zhao
IPC分类号： G03B23/02 , G11B20060101
CPC分类号： G03B23/02
摘要： A tape cartridge has a baseplate surrounded by a housing. Two hub pins are disposed within the housing substantially perpendicular to the baseplate. Each pin has top and bottom portions and a collared portion therebetween. The bottom portion of each pin is press-fitted into a mating aperture in the baseplate with the collared portion bearing against the baseplate. A large diameter tape hub is rotatably mounted on the top portion. The collared portions allow the hub pins to withstand heavy side loads without significantly deflecting from the perpendicular. Two large diameter tape hubs are rotatably mounted around the hub pins and improve the empty hub to full pack diameter ratios, and improve the resulting tangential drive force and tape tension profiles as the tape moves between the hubs. A back set of belt rollers includes a high-drag roller that engages the drive belt at a fixed wrap angle and produces a relatively constant drag. A front set of belt rollers includes a drive roller and has rollers mounted to form substantially equal geometries with rollers in the back set relative to the tape hubs. The constant wrap angle of a drive belt on the high-drag roller tends to outweigh varying drags from other rollers, causing less change in tape tension and tangential drive force as the tape is transferred from hub to hub in response to movement of the drive belt along a path in contact with the drive roller, the belt rollers, and the tape on the hubs.
摘要翻译：磁带盒具有由壳体包围的基板。两个毂销布置在壳体内基本垂直于底板。每个销具有顶部和底部以及它们之间的套环部分。每个销的底部被压配合到基板中的配合孔中，其中轴环部分抵靠基板。大直径磁带轮毂可旋转地安装在顶部上。轴环部分允许轮毂销承受重的侧向载荷，而不会明显地偏离垂直。两个大直径的磁带轮毂可旋转地安装在轮毂销周围，并将空的轮毂改善成全包装直径比，并且随着带在轮毂之间移动而改善所产生的切向驱动力和带张力轮廓。背面的一组皮带辊包括一个高牵引辊，它以固定的包角接合传动带并产生相对恒定的阻力。前一组皮带辊包括驱动辊，并且具有安装的辊，以形成与后背组中的辊相对于带轮毂大致相等的几何形状。驱动带在高牵引辊上的恒定包角倾向于超过其它辊的变化的拖动，从而当带根据传动带的移动将带从轮毂转移到轮毂时，带张力和切向驱动力的变化较小沿着与驱动辊，带辊和轮毂上的带接触的路径。

65. 发明申请

US20190101776A1 LIQUID CRYSTAL DISPLAY PANEL AND COMMON VOLTAGE COMPENSATION METHOD, DEVICE THEREOF 审中-公开
公开(公告)号：US20190101776A1
公开(公告)日：2019-04-04
申请号：US15545714
申请日：2017-05-10
申请人： Li ZHAO
发明人： Li ZHAO
IPC分类号： G02F1/133 , G09G3/36 , H01L27/12
摘要： Disclosed is a liquid crystal display panel, comprising an array substrate and a common voltage compensation circuit. The array substrate comprises scan lines, data lines, common electrode lines and sub pixel units arranged in array. The scan lines provide driving voltages to the sub pixel units, and the data lines provide data voltages to the sub pixel units, and the common electrode lines provide common voltages to the sub pixel units. The common voltage compensation circuit comprises a feedback signal processor, an amplifier and a common voltage adjusting circuit, and the feedback signal processor is connected to the common electrode lines to obtain feedback signals of the common voltages, and the amplifier implements an amplifying process to the feedback signals after inversion to obtain compensation signals, and the common voltage adjusting circuit inputs the compensation signals to the common electrode lines.

66. 发明授权

US09268611B2 Application scheduling in heterogeneous multiprocessor computing platform based on a ratio of predicted performance of processor cores 有权
标题翻译：基于处理器核心预测性能比例的异构多处理器计算平台中的应用调度
公开(公告)号：US09268611B2
公开(公告)日：2016-02-23
申请号：US12890653
申请日：2010-09-25
申请人： Ravishankar Iyer , Sadagopan Srinivasan , Li Zhao , Rameshkumar G. Illikkal
发明人： Ravishankar Iyer , Sadagopan Srinivasan , Li Zhao , Rameshkumar G. Illikkal
IPC分类号： G06F9/50 , G06F11/34 , G06F12/08
CPC分类号： G06F9/4881 , G06F9/5027 , G06F11/3409 , G06F11/3433 , G06F12/084 , G06F2201/88 , G06N5/02 , Y02D10/13 , Y02D10/22 , Y02D10/34
摘要： Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.
摘要翻译：描述了在异构多处理器计算平台中调度应用程序的方法和装置。在一个实施例中，处理器的多个处理器核的性能（例如，执行性能和/或功耗性能）的信息被存储（并被跟踪）在计数器和/或表中。处理器中的逻辑根据存储的信息确定哪个处理器内核应该执行应用程序。还要求和公开其它实施例。

67. 发明授权

US09258699B2 Method for route transmission based on single IPv6 address prefix, and wireless device 有权
标题翻译：基于单一IPv6地址前缀的路由传输方法和无线设备
公开(公告)号：US09258699B2
公开(公告)日：2016-02-09
申请号：US14241989
申请日：2012-02-17
申请人： Li Zhao , Tao Lu , Jianfeng Li , Xiaoliang Ma
发明人： Li Zhao , Tao Lu , Jianfeng Li , Xiaoliang Ma
IPC分类号： H04W8/26 , H04W80/04 , H04L29/12 , H04L29/06 , H04W84/18 , H04L12/741 , H04W40/24
CPC分类号： H04W8/26 , H04L45/74 , H04L61/2007 , H04L61/25 , H04L61/6004 , H04L61/6022 , H04L61/6059 , H04L61/6068 , H04L61/6077 , H04L61/6086 , H04L69/16 , H04W40/24 , H04W80/04 , H04W84/18
摘要： The present document provides a method and wireless device for implementing route transmission based on a single IPv6 address prefix. The method includes: when a wireless device succeeds in IPv6-based dialing and obtains one 64-bit-long IPv6 address prefix from a network side, the wireless device first setting apart a 126-bit IPv6 address prefix from the prefix, and then allocating the 126-bit IPv6 address prefix to a WAN interface, allocating the 64-bit-long IPv6 address prefix to a LAN interface, and notifying a user terminal connected to the LAN interface of the IPv6 prefix of the LAN interface, so that the user terminal connected to the LAN interface generates its own IPv6 address through a stateless address auto-configuration mechanism for communication. With the technical solutions of the present document, in an IPv4/IPv6 dual stack mode, IPv4 and IPv6 protocol stacks operate normally, and the radio resource consumption is reduced.
摘要翻译：本文提供了一种基于单个IPv6地址前缀实现路由传输的方法和无线设备。该方法包括：当无线设备成功进行基于IPv6的拨号并从网络侧获取一个64位长的IPv6地址前缀时，无线设备首先从前缀中分离出126比特的IPv6地址前缀，然后分配向WAN接口提供126位IPv6地址前缀，将64位长的IPv6地址前缀分配给LAN接口，并将连接到LAN接口的用户终端通知LAN接口的IPv6前缀，以便用户连接到LAN接口的终端通过无状态地址自动配置机制生成自己的IPv6地址进行通信。通过本文档的技术方案，在IPv4 / IPv6双栈模式下，IPv4和IPv6协议栈运行正常，无线资源消耗减少。

68. 发明授权

US08458711B2 Quality of service implementation for platform resources 有权
标题翻译：平台资源服务质量实施
公开(公告)号：US08458711B2
公开(公告)日：2013-06-04
申请号：US11527222
申请日：2006-09-25
申请人： Ramesh G. Illikkal , Ravishankar R. Iyer , Leena K. Puthiyedath , Donald K. Newell , Li Zhao , Srihari Makineni
发明人： Ramesh G. Illikkal , Ravishankar R. Iyer , Leena K. Puthiyedath , Donald K. Newell , Li Zhao , Srihari Makineni
IPC分类号： G06F9/46
CPC分类号： G06F9/5038 , G06F2209/5021
摘要： A method, computer readable medium, and system are disclosed. In one embodiment, the method comprises setting a quality of service (QoS) priority level value for one or more computer system platform resources, other than a central processor core, relating to a task running on the computer system, and determining whether the one or more computer system platform resources will be allocated to the task based on the QoS priority level setting.
摘要翻译：公开了一种方法，计算机可读介质和系统。在一个实施例中，该方法包括为与在计算机系统上运行的任务相关的一个或多个计算机系统平台资源（除了中央处理器核心）之外的一个或多个计算机系统平台资源设置服务质量（QoS）优先级值，基于QoS优先级设置，将更多的计算机系统平台资源分配给任务。

69. 发明申请

US20110161595A1 CACHE MEMORY POWER REDUCTION TECHNIQUES 有权
标题翻译：缓存记忆功率降低技术
公开(公告)号：US20110161595A1
公开(公告)日：2011-06-30
申请号：US12647461
申请日：2009-12-26
申请人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
发明人： Zhen Fang , Meenakshisundara R. Chinthamani , Li Zhao , Milind B. Kamble , Ravishankar Iyer , Seung Eun Lee , Robert S. Chappell , Ryan L. Carlson
IPC分类号： G06F12/08 , G06F12/00 , G06F1/32
CPC分类号： G06F12/0864 , G06F1/3225 , G06F1/3275 , G06F12/0895 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
摘要翻译：描述了提供存储器（诸如高速缓存存储器）中的功耗降低的方法和装置。在一个实施例中，使用虚拟标签来确定是否访问缓存方式。虚拟标签访问和比较可以在读取管道中比实际标签访问或比较更早地进行。在另一个实施例中，可以基于ECC前部分标签匹配来使用推测方式命中来唤醒数据阵列的子集。还描述了其它实施例。

70. 发明申请

US20110087843A1 Monitoring cache usage in a distributed shared cache 有权
标题翻译：监控分布式共享缓存中的缓存使用情况
公开(公告)号：US20110087843A1
公开(公告)日：2011-04-14
申请号：US12587670
申请日：2009-10-09
申请人： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
发明人： Li Zhao , Ravishankar Iyer , Rameshkumar G. Illikkal , Erik G. Hallnor , Martin G. Dixon , Donald K. Newell
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864
摘要： An apparatus, method, and system are disclosed. In one embodiment the apparatus includes a cache memory, which a number of sets. Each of the sets in the cache memory have several cache lines. The apparatus also includes at least one process resource table. The process resource table maintains a cache line occupancy count of a number of cache lines. Specifically, the cache line occupancy count for each cache line describes the number of cache lines in the cache storing information utilized by a process running on a computer system. Additionally, the process resource table stores the occupancy count of less cache lines than the total number of cache lines in the cache memory.
摘要翻译：公开了一种装置，方法和系统。在一个实施例中，该装置包括多个组的高速缓冲存储器。高速缓冲存储器中的每个集合具有多个高速缓存行。该装置还包括至少一个进程资源表。进程资源表维护多个高速缓存行的高速缓存行占用数。具体地说，每个高速缓存行的高速缓存线占用率表示高速缓存存储由计算机系统上运行的进程使用的信息的高速缓存行数。此外，处理资源表存储比高速缓冲存储器中的高速缓存行总数少的高速缓存行的占用数。

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