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1. 发明申请

US20170084326A1 A NEGATIVE DIFFERENTIAL RESISTANCE BASED MEMORY 审中-公开
公开(公告)号：US20170084326A1
公开(公告)日：2017-03-23
申请号：US15126255
申请日：2014-07-08
申请人： Daniel H. Morris , Uygar E. Avci , Rafael Rios , Ian A. Young
发明人： Daniel H. Morris , Uygar E. Avci , Rafael Rios , Ian A. Young
IPC分类号： G11C11/38 , H01L27/105 , H01L27/102 , G11C11/412
CPC分类号： G11C11/38 , G11C11/404 , G11C11/412 , H01L27/102 , H01L27/1021 , H01L27/1052 , H01L29/7391 , H01L29/885
摘要： Described is a memory bit-cell comprising: a storage node; an access transistor coupled to the storage node; a capacitor having a first terminal coupled to the storage node; and one or more negative differential resistance devices coupled to the storage node such that the memory bit-cell is without one of a ground line or a supply line or both.

2. 发明授权

US09583487B2 Semiconductor device having metallic source and drain regions 有权
标题翻译：具有金属源极和漏极区域的半导体器件
公开(公告)号：US09583487B2
公开(公告)日：2017-02-28
申请号：US13995419
申请日：2011-12-19
申请人： Martin D. Giles , Annalisa Cappellani , Sanaz Kabehie , Rafael Rios , Cory E. Weber , Aaron A. Budrevich
发明人： Martin D. Giles , Annalisa Cappellani , Sanaz Kabehie , Rafael Rios , Cory E. Weber , Aaron A. Budrevich
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/78 , H01L27/092 , H01L27/088 , H01L29/06
CPC分类号： H01L29/7848 , H01L21/2225 , H01L21/2254 , H01L21/2257 , H01L21/2258 , H01L21/28518 , H01L21/28556 , H01L21/28593 , H01L21/30608 , H01L21/30617 , H01L21/3065 , H01L21/823814 , H01L21/823821 , H01L27/088 , H01L27/092 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/401 , H01L29/456 , H01L29/66636 , H01L29/66795 , H01L29/7839 , H01L29/7845 , H01L29/785 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
摘要翻译：描述具有金属源极和漏极区域的半导体器件。例如，半导体器件包括设置在衬底的半导体沟道区域上方的栅电极堆叠。金属源区和漏区设置在衬底的上方，位于半导体沟道区的任一侧。金属源极和漏极区域中的每个具有轮廓。第一半导体外扩散区域设置在衬底中，在半导体沟道区域和金属源极区域之间，并与金属源极区域的形状保持一致。第二半导体外扩散区域设置在衬底中，在半导体沟道区域和金属漏极区域之间，并与金属漏极区域的轮廓保形。

3. 发明授权

US09425212B2 Isolated and bulk semiconductor devices formed on a same bulk substrate 有权
标题翻译：形成在同一块体基板上的隔离和体半导体器件
公开(公告)号：US09425212B2
公开(公告)日：2016-08-23
申请号：US13538822
申请日：2012-06-29
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Harry Gomez
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Harry Gomez
IPC分类号： H01L27/088 , H01L21/76 , H01L27/12 , H01L21/762
CPC分类号： H01L21/76237 , H01L21/76232 , H01L27/088 , H01L27/1207 , H01L29/0638 , H01L29/0653 , H01L29/7851
摘要： Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.
摘要翻译：描述了形成在相同体积基板上的隔离和体半导体器件以及形成这种器件的方法。例如，半导体结构包括具有设置在体基板上的第一半导体本体的第一半导体器件。第一半导体本体具有带有第一水平面的最上表面。半导体结构还包括具有设置在隔离基座上的第二半导体本体的第二半导体器件。隔离基座设置在主体基板上。第二半导体本体具有带有第二水平面的最上表面。第一和第二水平面是共面的。

4. 发明授权

US09362074B2 Nanowire-based mechanical switching device 有权
标题翻译：基于纳米线的机械开关装置
公开(公告)号：US09362074B2
公开(公告)日：2016-06-07
申请号：US13996507
申请日：2013-03-14
申请人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
发明人： Chytra Pawashe , Kevin Lin , Anurag Chaudhry , Raseong Kim , Seiyon Kim , Kelin Kuhn , Sasikanth Manipatruni , Rafael Rios , Ian A. Young
IPC分类号： H01H51/22 , H01H59/00 , B82Y10/00 , H01H1/00 , H01H9/02
CPC分类号： H01L29/84 , B82Y10/00 , H01H1/0094 , H01H9/0271 , H01H59/0009 , H01L29/045 , H01L29/0673 , H01L29/161
摘要： Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The nanowire has an anchored portion and a suspended portion. A first gate electrode is disposed adjacent the void, and is spaced apart from the nanowire. A first conductive region is disposed adjacent the first gate electrode and adjacent the void, and is spaced apart from the nanowire.
摘要翻译：描述了基于纳米线的机械开关装置。例如，纳米线继电器包括布置在衬底上方的空隙中的纳米线。纳米线具有锚固部分和悬挂部分。第一栅电极邻近空隙设置，并与纳米线隔开。第一导电区域邻近第一栅电极设置并邻近空隙，并与纳米线隔开。

5. 发明申请

US20160086951A1 CMOS NANOWIRE STRUCTURE 审中-公开
标题翻译： CMOS纳米结构
公开(公告)号：US20160086951A1
公开(公告)日：2016-03-24
申请号：US14948083
申请日：2015-11-20
申请人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
发明人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/423 , H01L29/06 , H01L29/10
CPC分类号： H01L21/823821 , B82Y10/00 , H01L21/8238 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/12 , H01L27/1203 , H01L27/1211 , H01L29/0673 , H01L29/0676 , H01L29/1033 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/7853
摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
摘要翻译：描述了免费的金属氧化物半导体纳米线结构。例如，半导体结构包括第一半导体器件。第一半导体器件包括设置在衬底之上的第一纳米线。第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一栅极电极堆叠完全包围第一纳米线的离散通道区域。半导体结构还包括第二半导体器件。第二半导体器件包括设置在衬底上方的第二纳米线。第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一距离与第二距离不同。第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

6. 发明授权

US08890120B2 Tunneling field effect transistors (TFETs) for CMOS approaches to fabricating N-type and P-type TFETs 有权
标题翻译：用于CMOS方法的隧道场效应晶体管（TFET）用于制造N型和P型TFET
公开(公告)号：US08890120B2
公开(公告)日：2014-11-18
申请号：US13678867
申请日：2012-11-16
申请人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
发明人： Roza Kotlyar , Stephen M. Cea , Gilbert Dewey , Benjamin Chu-Kung , Uygar E. Avci , Rafael Rios , Anurag Chaudhry , Thomas D. Linton, Jr. , Ian A. Young , Kelin J. Kuhn
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/66977 , H01L27/092 , H01L29/045 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/20 , H01L29/24 , H01L29/267 , H01L29/42392 , H01L29/7391 , H01L29/7842 , H01L29/785 , H01L29/78603 , H01L29/78642 , H01L29/78684 , H01L29/78696
摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.
摘要翻译：描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。栅极堆叠包括栅极电介质部分和栅极电极部分。

7. 发明申请

US20140001560A1 ISOLATED AND BULK SEMICONDUCTOR DEVICES FORMED ON A SAME BULK SUBSTRATE 有权
标题翻译：在相同的大块基板上形成的隔离和大块半导体器件
公开(公告)号：US20140001560A1
公开(公告)日：2014-01-02
申请号：US13538822
申请日：2012-06-29
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Harry Gomez
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Harry Gomez
IPC分类号： H01L27/088 , H01L21/76
CPC分类号： H01L21/76237 , H01L21/76232 , H01L27/088 , H01L27/1207 , H01L29/0638 , H01L29/0653 , H01L29/7851
摘要： Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.
摘要翻译：描述了形成在相同体积基板上的隔离和体半导体器件以及形成这种器件的方法。例如，半导体结构包括具有设置在体基板上的第一半导体本体的第一半导体器件。第一半导体本体具有带有第一水平面的最上表面。半导体结构还包括具有设置在隔离基座上的第二半导体本体的第二半导体器件。隔离基座设置在主体基板上。第二半导体本体具有带有第二水平面的最上表面。第一和第二水平面是共面的。

8. 发明申请

US20090020792A1 ISOLATED TRI-GATE TRANSISTOR FABRICATED ON BULK SUBSTRATE 审中-公开
标题翻译：隔离三极晶体管在大块基板上制作
公开(公告)号：US20090020792A1
公开(公告)日：2009-01-22
申请号：US11779284
申请日：2007-07-18
申请人： Rafael Rios , Jack Kavalieros , Stephen M. Cea
发明人： Rafael Rios , Jack Kavalieros , Stephen M. Cea
IPC分类号： H01L29/78 , H01L21/02
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of forming an isolated tri-gate semiconductor body comprises patterning a bulk substrate to form a fin structure, depositing an insulating material around the fin structure, recessing the insulating material to expose a portion of the fin structure that will be used for the tri-gate semiconductor body, depositing a nitride cap over the exposed portion of the fin structure to protect the exposed portion of the fin structure, and carrying out a thermal oxidation process to oxidize an unprotected portion of the fin structure below the nitride cap. The oxidized portion of the fin isolates the semiconductor body that is being protected by the nitride cap. The nitride cap may then be removed. The thermal oxidation process may comprise annealing the substrate at a temperature between around 900° C. and around 1100° C. for a time duration between around 0.5 hours and around 3 hours.
摘要翻译：形成隔离的三栅极半导体器件的方法包括：图案化块状衬底以形成翅片结构，在鳍结构周围沉积绝缘材料，使绝缘材料凹陷以暴露将用于三极管的鳍结构的一部分 - 半导体本体，在所述鳍结构的暴露部分上沉积氮化物帽以保护所述鳍结构的暴露部分，以及执行热氧化工艺以将所述鳍状结构的未受保护的部分氧化在所述氮化物帽下方。翅片的氧化部分隔离被氮化物盖保护的半导体主体。然后可以去除氮化物盖。热氧化过程可以包括在大约900℃和大约1100℃之间的温度下退火约0.5小时至约3小时的时间。

9. 发明授权

US06489655B2 Integrated circuit with dynamic threshold voltage 有权
标题翻译：具有动态阈值电压的集成电路
公开(公告)号：US06489655B2
公开(公告)日：2002-12-03
申请号：US09782540
申请日：2001-02-12
申请人： Brian S. Doyle , Brian Roberds , Rafael Rios
发明人： Brian S. Doyle , Brian Roberds , Rafael Rios
IPC分类号： H01L2701
CPC分类号： H01L29/78621 , H01L29/78606 , H01L29/78696
摘要： An integrated circuit and method for making it are described. The integrated circuit includes a first insulating layer formed on a substrate and a body strap of a first conductivity type that is formed on the first insulating layer. A second insulating layer is formed on the first insulating layer adjacent to the body strap and a film is formed on the second insulating layer. The integrated circuit also includes a gate electrode formed on the film. A plurality of doped regions of a second conductivity type are formed within the film that extend from the surface of the film to the surface of the second insulating layer. The doped regions have junctions that are each spaced from the body strap by at least about 500 angstroms.
摘要翻译：对集成电路及其制作方法进行说明。集成电路包括形成在基板上的第一绝缘层和形成在第一绝缘层上的第一导电类型的主体带。在与体带相邻的第一绝缘层上形成第二绝缘层，并且在第二绝缘层上形成膜。集成电路还包括形成在膜上的栅电极。在薄膜内形成多个第二导电类型的掺杂区，从薄膜的表面延伸到第二绝缘层的表面。掺杂区域具有与体带相隔至少约500埃的交点。

10. 发明申请

US20170125591A1 SEMICONDUCTOR DEVICE HAVING METALLIC SOURCE AND DRAIN REGIONS 审中-公开
公开(公告)号：US20170125591A1
公开(公告)日：2017-05-04
申请号：US15408294
申请日：2017-01-17
申请人： Martin D. GILES , Annalisa CAPPELLANI , Sanaz KABEHIE , Rafael RIOS , Cory E. WEBER , Aaron A. BUDREVICH
发明人： Martin D. GILES , Annalisa CAPPELLANI , Sanaz KABEHIE , Rafael RIOS , Cory E. WEBER , Aaron A. BUDREVICH
IPC分类号： H01L29/78 , H01L29/08 , H01L29/167 , H01L29/66 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/2225 , H01L21/2254 , H01L21/2257 , H01L21/2258 , H01L21/28518 , H01L21/28556 , H01L21/28593 , H01L21/30608 , H01L21/30617 , H01L21/3065 , H01L21/823814 , H01L21/823821 , H01L27/088 , H01L27/092 , H01L29/0673 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/401 , H01L29/456 , H01L29/66636 , H01L29/66795 , H01L29/7839 , H01L29/7845 , H01L29/785 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.

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