专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08446170B2 FPGA RAM blocks optimized for use as register files 有权
标题翻译：优化的FPGA RAM块用作寄存器文件
公开(公告)号：US08446170B2
公开(公告)日：2013-05-21
申请号：US13463232
申请日：2012-05-03
申请人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
发明人： Joel Landry , Jonathan Greene , William C. Plants , Wenyi Feng
IPC分类号： H03K19/177
CPC分类号： H03K19/177 , G11C8/16 , H03K19/1776
摘要： A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
摘要翻译：公开了一种适用于现场可编程门阵列集成电路器件的随机存取存储器电路。 FPGA具有可编程阵列，其具有逻辑模块和路由互连，可编程地耦合到逻辑模块和RAM电路。 RAM电路具有三个端口：第一可读端口，第二可读端口和可写入端口。读端口可以是可编程同步的或异步的，并且具有可编程可旁路输出流水线寄存器。 RAM电路特别适用于实现寄存器文件。还描述了一种新颖的互连方法。

2. 发明授权

US08255854B2 Architecture and method for compensating for disparate signal rise and fall times by using polarity selection to improve timing and power in an integrated circuit 有权
标题翻译：通过使用极性选择来提高集成电路中的时序和功率来补偿不同信号上升和下降时间的架构和方法
公开(公告)号：US08255854B2
公开(公告)日：2012-08-28
申请号：US12753247
申请日：2010-04-02
申请人： Kai Zhu , Volker Hecht
发明人： Kai Zhu , Volker Hecht
IPC分类号： G06F17/50 , G06F9/455 , G06F7/38
CPC分类号： G06F17/5031 , G06F2217/78 , G06F2217/84
摘要： A method for reducing delay in an integrated circuit by compensating for differences in rise and fall delay times comprises creating a timing graph; computing minimum delay tuples for nodes in the timing graph; if there is not at least one feasible delay tuple, determining a longest path and computing minimum delay tuples for the longest path; changing polarities on the longest path to reduce delays; updating the timing graph by transferring new polarity and delay values; performing timing analysis to determine a new longest path if the new longest path is shorter than the prior longest path, accepting a resulting polarity selection and computing minimum delay tuples for the longest path; if the new longest path is not shorter than the prior longest path, accepting a resulting polarity selection and implementing changes in a user-program bitstream.
摘要翻译：通过补偿上升和下降延迟时间的差异来减少集成电路中的延迟的方法包括创建时序图; 计算定时图中节点的最小延迟元组; 如果不存在至少一个可行延迟元组，则确定最长路径并计算最长路径的最小延迟元组; 在最长的路径上改变极性以减少延误; 通过传递新的极性和延迟值来更新时序图; 执行定时分析以确定新的最长路径，如果新的最长路径短于先前的最长路径，则接受所得极性选择并计算最长路径的最小延迟元组; 如果新的最长路径不比先前最长的路径短，则接受所得到的极性选择并实现用户节目比特流中的改变。

3. 发明授权

US08191021B2 Single event transient mitigation and measurement in integrated circuits 有权
标题翻译：集成电路中的单事件瞬态缓解和测量
公开(公告)号：US08191021B2
公开(公告)日：2012-05-29
申请号：US12361955
申请日：2009-01-29
申请人： Sana Rezgui
发明人： Sana Rezgui
IPC分类号： G06F17/50 , G06F9/455 , H03K19/007 , H03K19/003 , H03K17/16
CPC分类号： H03K19/0033
摘要： A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. Provision is made for applying the method to logic designs implemented in programmable logic integrated circuit devices.
摘要翻译：描述了集成电路装置中的单事件瞬态滤波的方法。该装置包括三个顺序元件，每个元件具有数据输入和数据输出，其中三个数据输出中的每一个耦合到投票口的三个输入之一。该方法包括在第一和第二SET域中产生第一和第二名义上等效的逻辑信号，将第一和第二名义上等效的逻辑信号转换成第一，第二和第三名义上等效的数据信道，以及发送第一，第二和第三名义上等效的数据信道到第一，第二和第三顺序元件的数据输入。规定了将该方法应用于在可编程逻辑集成电路器件中实现的逻辑设计。

4. 发明授权

US07977970B2 Enhanced field programmable gate array 有权
标题翻译：增强型现场可编程门阵列
公开(公告)号：US07977970B2
公开(公告)日：2011-07-12
申请号：US12794279
申请日：2010-06-04
申请人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
发明人： Samuel W. Beal , Sinan Kaptanoglu , Jung-Cheun Lien , William Shu , King W. Chan , William C. Plants
IPC分类号： H03K19/177
CPC分类号： H03K19/17768 , H03K19/1736 , H03K19/17704 , H03K19/17732 , H03K19/17736 , H03K19/17744 , H03K19/17796
摘要： An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
摘要翻译：增强的性能现场可编程门阵列集成电路包括现场可编程门阵列和其它功能电路，例如同一集成电路中的掩模可编程门阵列。电路接口提供现场可编程门阵列，掩模可编程门阵列和集成电路I / O之间的通信。

5. 发明授权

US07937647B2 Error-detecting and correcting FPGA architecture 有权
标题翻译：错误检测和校正FPGA架构
公开(公告)号：US07937647B2
公开(公告)日：2011-05-03
申请号：US11829335
申请日：2007-07-27
申请人： Vidyadhara Bellipaddy , Gregory Bakker
发明人： Vidyadhara Bellipaddy , Gregory Bakker
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03K19/1776 , G06F11/1052 , G11C2029/0411 , H03K19/17764
摘要： A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated.
摘要翻译：提供了用于纠错FPGA的方法和装置。生成用于配置的ECC数据并将其编程到配置存储器中的ECC行中。在引导时，确定是否设置完整性校验位。如果是这样，则执行完整性检查。如果检测到单位错误，如果位错误是错误的“0”值，则包含错误“0”值的存储器位置被重新编程为“1”值。如果位错误是错误的“1”值，则存储器块数据被保存在非易失性存储器块中，包含该错误的配置存储器块被擦除并且使用校正位被重新编程。如果存在多个错误，则设置错误标志。用户通过JTAG端口读取错误标志的状态。如果设置了错误标志，则启动完整的重新编程周期。

6. 发明授权

US07911226B2 Power-up and power-down circuit for system-on-a-chip integrated circuit 有权
标题翻译：用于片上系统集成电路的上电和掉电电路
公开(公告)号：US07911226B2
公开(公告)日：2011-03-22
申请号：US11467279
申请日：2006-08-25
申请人： Gregory Bakker
发明人： Gregory Bakker
IPC分类号： H03K19/173 , G05F1/00 , G05F5/00
CPC分类号： G11C5/147 , H01L2924/0002 , H03K17/22 , Y10T307/50 , Y10T307/724 , H01L2924/00
摘要： A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.
摘要翻译：用于集成电路的上电和掉电电路包括用于第一电压的电压调节器。第一个I / O焊盘内部耦合到电压调节器和第一个内部电路的输入端。第二电压外部耦合到第一I / O焊盘。第二I / O焊盘内部耦合到被配置为驱动外部晶体管的基极的电压调节器的输出端。集成电路的第三个I / O焊盘内部耦合到电压调节器的参考电压输入端。第四I / O焊盘耦合到电压调节器的反馈输入端。集成电路的第五个I / O焊盘内部耦合到逻辑电路，该逻辑电路从包括设置在集成电路上的实时时钟电路的内部信号的内部信号控制集成电路的上电和掉电。

7. 发明授权

US07886261B1 Programmable logic device adapted to enter a low-power mode 有权
标题翻译：适于进入低功率模式的可编程逻辑器件
公开(公告)号：US07886261B1
公开(公告)日：2011-02-08
申请号：US11928445
申请日：2007-10-30
申请人： Kenneth Irving , Vishal Aggrawal , Prasad Karuganti
发明人： Kenneth Irving , Vishal Aggrawal , Prasad Karuganti
IPC分类号： G06F17/50
CPC分类号： H03K19/17784
摘要： A programmable logic integrated circuit device adapted to enter a low-power mode is described. The integrated circuit device includes a programmable logic block, a first low-power mode control circuit programmed into a portion of the programmable logic block, a second low-power mode control circuit, and a low-power enable input coupled to the first low-power mode control circuit and the second low-power mode control circuit. This arrangement allows the programmable logic integrated circuit device to transition into and out of low-power mode in response to a single signal from system control logic, so that the system control logic can be designed without detailed understanding of the inner workings of the programmable logic integrated circuit device or its programmed design.
摘要翻译：描述适于进入低功率模式的可编程逻辑集成电路装置。集成电路装置包括可编程逻辑块，被编程到可编程逻辑块的一部分中的第一低功率模式控制电路，第二低功率模式控制电路和耦合到第一低功率模式控制电路的低功率使能输入，功率模式控制电路和第二低功率模式控制电路。这种布置允许可编程逻辑集成电路器件响应于来自系统控制逻辑的单个信号而转换到和流出低功率模式，使得可以设计系统控制逻辑而无需详细了解可编程逻辑的内部工作集成电路器件或其编程设计。

8. 发明申请

US20110001115A1 RESISTIVE RAM DEVICES FOR PROGRAMMABLE LOGIC DEVICES 有权
标题翻译：用于可编程逻辑器件的电阻RAM器件
公开(公告)号：US20110001115A1
公开(公告)日：2011-01-06
申请号：US12829300
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L45/00
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer.
摘要翻译：形成在半导体衬底上的电阻性随机存取存储器件包括具有穿过其中形成的通孔的层间电介质。在层间电介质上形成化学机械抛光停止层。屏障金属衬垫线路通孔的墙壁。在通孔中形成导电塞。第一阻挡金属层形成在化学机械抛光停止层上并与导电塞电接触。在第一阻挡金属层上形成电介质层。在电介质层上形成离子源层。介电阻挡层形成在离子源层上，并且包括与离子源层连通的通孔。第二阻挡金属层形成在电介质阻挡层上并与离子源层电接触。金属互连层形成在阻挡金属层的上方。

9. 发明授权

US07774665B2 Apparatus for testing a phrase-locked loop in a boundary scan enabled device 有权
标题翻译：用于在边界扫描启用的设备中测试短语锁定环路的装置
公开(公告)号：US07774665B2
公开(公告)日：2010-08-10
申请号：US12198249
申请日：2008-08-26
申请人： Wei-Min Kuo , Donald Y. Yu
发明人： Wei-Min Kuo , Donald Y. Yu
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/3016
摘要： An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.
摘要翻译：用于将现场可编程门阵列中的锁相环接口的装置。该装置包括锁相环集群。所述锁相环还包括多个RT模块，多个RO模块，至少一个TY模块，多个接收模块和至少一个缓冲模块。锁相环选择性地耦合到RT模块，RO模块，TY模块，接收器模块和锁相环集群中的至少一个缓冲模块。

10. 发明申请

US20100156460A1 (N+1) INPUT FLIP-FLOP PACKING WITH LOGIC IN FPGA ARCHITECTURES 有权
标题翻译：（N + 1）在FPGA架构中使用逻辑输入FLOP-FLOP包装
公开(公告)号：US20100156460A1
公开(公告)日：2010-06-24
申请号：US12717315
申请日：2010-03-04
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/1737 , H03K19/17728
摘要： A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
摘要翻译：逻辑模块和触发器包括具有耦合到路由资源的数据输入的输入多路复用器。时钟复用器具有耦合到时钟资源的输入和输出。输入选择多路复用器具有耦合到输入多路复用器的输出的第一输入。触发器具有耦合到时钟复用器的输出的时钟输入和耦合到输入选择多路复用器的输入的数据输出。逻辑模块具有耦合到输入选择多路复用器的输出的数据输入。触发器多路复用器耦合到触发器的数据输入，并具有耦合到第一输入多路复用器的输出，逻辑模块的数据输出和耦合到路由资源的第三输入的输入输入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式